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140 lines
3.9 KiB
Verilog
140 lines
3.9 KiB
Verilog
/*
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File: e_tx_protocol.v
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This file is part of the Parallella Project.
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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/*
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########################################################################
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EPIPHANY eLink TX Protocol block
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########################################################################
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This block takes standard eMesh protocol (104-bit transactions) and
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encodes the bytes into 8-byte parallel outputs for the output
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serializers.
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*/
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module etx_protocol (/*AUTOARG*/
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// Outputs
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e_tx_rd_wait, e_tx_wr_wait, e_tx_ack, txframe_p, txdata_p,
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// Inputs
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reset, e_tx_access, e_tx_write, e_tx_datamode, e_tx_ctrlmode,
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e_tx_dstaddr, e_tx_srcaddr, e_tx_data, txlclk_p, tx_rd_wait,
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tx_wr_wait
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);
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// System reset input
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input reset;
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// Input from TX Arbiter
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input e_tx_access;
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input e_tx_write;
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input [1:0] e_tx_datamode;
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input [3:0] e_tx_ctrlmode;
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input [31:0] e_tx_dstaddr;
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input [31:0] e_tx_srcaddr;
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input [31:0] e_tx_data;
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output e_tx_rd_wait;
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output e_tx_wr_wait;
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output e_tx_ack;
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// Parallel interface, 8 eLink bytes at a time
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input txlclk_p; // Parallel-rate clock from eClock block
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output [7:0] txframe_p;
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output [63:0] txdata_p;
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input tx_rd_wait; // The wait signals are passed through
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input tx_wr_wait; // to the emesh interfaces
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//#############
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//# Configuration bits
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//#############
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//############
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//# Local regs & wires
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//############
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reg e_tx_ack; // Acknowledge transaction
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reg [7:0] txframe_p;
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reg [63:0] txdata_p;
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//############
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//# Logic
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//############
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// TODO: Bursts
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always @( posedge txlclk_p or posedge reset ) begin
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if( reset ) begin
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e_tx_ack <= 1'b0;
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txframe_p <= 'd0;
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txdata_p <= 'd0;
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end else begin
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if( e_tx_access & ~e_tx_ack ) begin
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e_tx_ack <= 1'b1;
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txframe_p <= 8'h3F;
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txdata_p <=
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{ 8'd0, // Not used
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8'd0,
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~e_tx_write, 7'd0, // B0- TODO: For bursts, add the inc bit
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e_tx_ctrlmode, e_tx_dstaddr[31:28], // B1
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e_tx_dstaddr[27:4], // B2, B3, B4
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e_tx_dstaddr[3:0], e_tx_datamode, e_tx_write, e_tx_access // B5
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};
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end else if( e_tx_ack ) begin // if ( e_tx_access & ~e_tx_ack )
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e_tx_ack <= 1'b0;
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txframe_p <= 8'hFF;
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txdata_p <= { e_tx_data, e_tx_srcaddr };
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end else begin
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e_tx_ack <= 1'b0;
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txframe_p <= 8'h00;
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txdata_p <= 64'd0;
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end
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end // else: !if( reset )
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end // always @ ( posedge txlclk_p or reset )
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//#############################
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//# Wait signals
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//#############################
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reg rd_wait_sync;
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reg wr_wait_sync;
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reg e_tx_rd_wait;
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reg e_tx_wr_wait;
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always @( posedge txlclk_p ) begin
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rd_wait_sync <= tx_rd_wait;
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e_tx_rd_wait <= rd_wait_sync;
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wr_wait_sync <= tx_wr_wait;
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e_tx_wr_wait <= wr_wait_sync;
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end
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endmodule // e_tx_protocol
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