Andreas Olofsson b0b9315bf1 Massive checkin... ...

-this may break already broken projects
-creates a Verilog top level (instead of using Vivado block level design)
-integrates mmy and mailbox (not completely integrated)
-compiles...
-pours in all of the code from the archive
(some new logic created)

2015-03-24 20:44:03 -04:00

..

BUFG.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

BUFIO.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

BUFR.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

IBUFDS.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

IBUFGDS.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

ISERDESE2.v

Revert "Fixing port declarations (thanks Verilator!)"

2015-01-28 14:15:13 -05:00

OBUFDS.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

OBUFTDS.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

ODDR.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

OSERDESE2.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

PLLE2_BASE.v

Revert "Fixing port declarations (thanks Verilator!)"

2015-01-28 14:15:13 -05:00