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oh/stubs/hdl/BUFIO.v
aolofsson 47fa7ff23d Adding stubs files for xilinx IP
Goal is to create models for all of these
2014-12-14 22:21:01 -05:00

12 lines
119 B
Verilog

module BUFIO (/*AUTOARG*/
// Outputs
O,
// Inputs
I
);
input I;
output O;
endmodule // BUFIO