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Goal is to create models for all of these
22 lines
260 B
Verilog
22 lines
260 B
Verilog
module OBUFDS (/*AUTOARG*/
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// Outputs
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O, OB,
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// Inputs
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I
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);
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parameter DIFF_TERM=0;
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parameter IOSTANDARD=0;
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parameter SLEW=0;
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input I;
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output O;
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output OB;
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assign O = I;
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assign OB = ~I;
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endmodule // OBUFDS
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