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oh/stubs/hdl/OBUFDS.v
aolofsson 47fa7ff23d Adding stubs files for xilinx IP
Goal is to create models for all of these
2014-12-14 22:21:01 -05:00

22 lines
260 B
Verilog

module OBUFDS (/*AUTOARG*/
// Outputs
O, OB,
// Inputs
I
);
parameter DIFF_TERM=0;
parameter IOSTANDARD=0;
parameter SLEW=0;
input I;
output O;
output OB;
assign O = I;
assign OB = ~I;
endmodule // OBUFDS