Andreas Olofsson b1a9f502ca Xilinx models ...

-adding ODDR model
-configuring the ecfg (rx/tx/clk) in testbench

2015-04-15 17:54:19 -04:00

..

axi_bram_ctrl_16b.v

Adding stubs for IP blocks used in elink

2015-04-08 23:38:36 -04:00

BUFG.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

BUFIO.v

Vivado run through

2015-04-08 23:40:16 -04:00

BUFR.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

fifo_async_103x16.v

Adding stubs for IP blocks used in elink

2015-04-08 23:38:36 -04:00

fifo_async_103x32.v

Adding stubs for IP blocks used in elink

2015-04-08 23:38:36 -04:00

fifo_async_104x16.v

Adding missing stubs

2015-04-14 09:42:19 -04:00

fifo_async_104x32.v

Verilator lint cleanup

2015-04-14 14:00:23 -04:00

IBUFDS.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

IBUFGDS.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

ISERDESE2.v

Major cleanup, refactoring, and feature completion

2015-04-11 00:04:18 -04:00

memory_dp_48x4096.v

Adding stubs for IP blocks used in elink

2015-04-08 23:38:36 -04:00

OBUFDS.v

Adding stubs files for xilinx IP

2014-12-14 22:21:01 -05:00

OBUFTDS.v

Xilinx models

2015-04-15 17:54:19 -04:00

ODDR.v

Xilinx models

2015-04-15 17:54:19 -04:00

OSERDESE2.v

Vivado run through

2015-04-08 23:40:16 -04:00

PLLE2_BASE.v

Major cleanup, refactoring, and feature completion

2015-04-11 00:04:18 -04:00

RAM32X1D.v

Adding stubs for IP blocks used in elink

2015-04-08 23:38:36 -04:00