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42 lines
857 B
Verilog
42 lines
857 B
Verilog
module ODDR (/*AUTOARG*/
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// Outputs
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Q,
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// Inputs
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C, CE, D1, D2, R, S
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);
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parameter DDR_CLK_EDGE=0; //clock recovery mode
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parameter INIT=0; //Q init value
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parameter SRTYPE=0;//"SYNC", "ASYNC"
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input C; // Clock input
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input CE; // Clock enable input
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input D1; // Data input1
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input D2; // Data input2
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input R; // Reset (depends on SRTYPE)
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input S; // Active high asynchronous pin
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output Q; // Data Output that connects to the IOB pad
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reg Q1,Q2;
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//Generate different logic based on parameters
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//Only doing same edge and async reset for now
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always @ (posedge C or posedge R)
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if (R)
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Q1 <= 1'b0;
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else
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Q1 <= D1;
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always @ (posedge C or posedge R)
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if (R)
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Q2 <= 1'b0;
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else
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Q2 <= D2;
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assign Q = C ? Q1 : Q2;
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endmodule // ODDR
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