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https://github.com/aolofsson/oh.git
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73229ff914
-adding clock bypass mode for esystx[12] -removing monitor feature on erx -remove loopback support from doc -add clock bypass mode for esysclk -shortening register names (descriptive enough) -added debug signal information -moving registers to elink -making elink version programmable (to support plug in boards) -reorganized debug signals and added stickys -added timeout for axi slave -removed embox status bit (redudant, don't poll status) -renamed EMBOX0-->EMBOXLO -moved datain interface straight to ecfg (cleanup) -changed etx arbiter priority to increase stability -created the esaxi_mux block -fixed some missing ports issues in stubs Now comes the fun part...verification... Andreas
72 lines
1.6 KiB
Verilog
72 lines
1.6 KiB
Verilog
module PLLE2_BASE (/*AUTOARG*/
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// Outputs
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LOCKED, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5,
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CLKFBOUT,
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// Inputs
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CLKIN1, RST, PWRDWN, CLKFBIN
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);
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parameter BANDWIDTH = 0;
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parameter CLKFBOUT_MULT = 0;
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parameter CLKFBOUT_PHASE = 0;
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parameter CLKIN1_PERIOD = 0;
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parameter CLKOUT0_DIVIDE = 0;
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parameter CLKOUT0_DUTY_CYCLE = 0;
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parameter CLKOUT0_PHASE = 0;
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parameter CLKOUT1_DIVIDE = 0;
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parameter CLKOUT1_DUTY_CYCLE = 0;
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parameter CLKOUT1_PHASE = 0;
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parameter CLKOUT2_DIVIDE = 0;
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parameter CLKOUT2_DUTY_CYCLE = 0;
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parameter CLKOUT2_PHASE = 0;
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parameter CLKOUT3_DIVIDE = 0;
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parameter CLKOUT3_DUTY_CYCLE = 0;
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parameter CLKOUT3_PHASE = 0;
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parameter CLKOUT4_DIVIDE = 0;
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parameter CLKOUT4_DUTY_CYCLE = 0;
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parameter CLKOUT4_PHASE = 0;
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parameter CLKOUT5_DIVIDE = 0;
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parameter CLKOUT5_DUTY_CYCLE = 0;
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parameter CLKOUT5_PHASE = 0;
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parameter DIVCLK_DIVIDE = 0;
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parameter REF_JITTER1 = 0;
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parameter STARTUP_WAIT = 0;
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parameter IOSTANDARD = 0;
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//inputs
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input CLKIN1;
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input RST;
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input PWRDWN;
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input CLKFBIN;
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//outputs
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output LOCKED;
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output CLKOUT0;
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output CLKOUT1;
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output CLKOUT2;
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output CLKOUT3;
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output CLKOUT4;
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output CLKOUT5;
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output CLKFBOUT;
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//Not a correct model
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assign CLKFBOUT=CLKIN1;
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assign LOCKED=1'b0;
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assign CLKOUT0=CLKIN1;
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assign CLKOUT1=CLKIN1;
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assign CLKOUT2=CLKIN1;
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assign CLKOUT3=CLKIN1;
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assign CLKOUT4=CLKIN1;
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assign CLKOUT5=CLKIN1;
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assign CLKFBOUT=CLKIN1;
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endmodule // PLLE2_BASE
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