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30 lines
420 B
Verilog
30 lines
420 B
Verilog
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module memory_dp_48x4096 (/*AUTOARG*/
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// Outputs
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doutb,
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// Inputs
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clka, ena, wea, addra, dina, clkb, enb, addrb
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);
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//write
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input clka;
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input ena;
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input [5:0] wea;
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input [11:0] addra;
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input [47:0] dina;
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//read
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input clkb;
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input enb;
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input [11:0] addrb;
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output [47:0] doutb;
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assign doutb[47:0]=48'b0;
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endmodule // memory_dp_48x4096
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