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846bfa3357
-adding reset signals to synchronizer to solve startup issues -setting config in test bench for speedup, default reg config now correct -fix (my) stupid bug in etx_arbiter -adding reset to fifo (todo: review this!) -reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.
61 lines
1.5 KiB
Verilog
61 lines
1.5 KiB
Verilog
/*
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#######################################################
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# Synchronizer circuit
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#######################################################
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*/
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module synchronizer (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in, clk, reset
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);
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parameter DW = 32;
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//Input Side
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input [DW-1:0] in;
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input clk;
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input reset;
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//Output Side
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output [DW-1:0] out;
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//Three stages
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reg [DW-1:0] sync_reg0;
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reg [DW-1:0] out;
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//We use two flip-flops for metastability improvement
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always @ (posedge clk or posedge reset)
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if(reset)
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begin
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sync_reg0[DW-1:0] <= {(DW){1'b0}};
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out[DW-1:0] <= {(DW){1'b0}};
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end
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else
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begin
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sync_reg0[DW-1:0] <= in[DW-1:0];
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out[DW-1:0] <= sync_reg0[DW-1:0];
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end
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endmodule // synchronizer
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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