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72 lines
2.1 KiB
Verilog
72 lines
2.1 KiB
Verilog
/*
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Copyright (C) 2015 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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/*
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########################################################################
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Generic asynchronous FIFO
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Caution: There is no protection against overflow or underflow,
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driving logic should avoid wen on full or ren on empty.
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########################################################################
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*/
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module fifo_async(/*AUTOARG*/
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// Outputs
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wr_full, wr_progfull, rd_data, rd_empty,
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// Inputs
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reset, wr_clk, wr_en, wr_data, rd_clk, rd_en
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);
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parameter AW = 5; //fifo address width
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parameter DW = 16; //fifo data width
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//Reset
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input reset;
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//Write side interface
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input wr_clk; //write side clock
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input wr_en; //write enable
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input [DW-1:0] wr_data; //write data
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output wr_full; //fifo full
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output wr_progfull; //programmable full level
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//Read side interface
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input rd_clk; //read side clock
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input rd_en; //read enable
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output [DW-1:0] rd_data; //read data
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output rd_empty; //fifo empty
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//Dummy for now...
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assign rd_data = 103'b0;
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assign rd_empty = 1'b0;
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assign wr_full = 1'b0;
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assign wr_progfull = 1'b0;
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//TODO:instatiate the right fifo
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//distributed RAM
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//32 x 103
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//async reset signal, assert high, full asserted on 16
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endmodule // fifo_async
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