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123 lines
3.4 KiB
Verilog
123 lines
3.4 KiB
Verilog
//`include "elink_regmap.v"
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module dut(/*AUTOARG*/
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// Outputs
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dut_active, clkout, wait_out, access_out, packet_out,
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// Inputs
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clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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//##########################################################################
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//# INTERFACE
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//##########################################################################
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parameter AW = 32;
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parameter ID = 12'h810;
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parameter S_IDW = 12;
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parameter M_IDW = 6;
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parameter PW = 2*AW + 40;
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parameter N = 1;
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parameter IRQW = 10;
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parameter LAW = 16;
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//clock,reset
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input clk1;
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input clk2;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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output clkout;
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transaction
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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//####################################################################
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//#BODY
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//####################################################################
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wire mem_rd_wait;
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wire mem_wr_wait;
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wire mem_access;
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wire [PW-1:0] mem_packet;
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/*AUTOINPUT*/
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wire ic_flush; // From pic of pic.v
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wire [IRQW-1:0] ic_ilat_reg; // From pic of pic.v
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wire [IRQW-1:0] ic_imask_reg; // From pic of pic.v
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wire [IRQW-1:0] ic_ipend_reg; // From pic of pic.v
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wire [LAW-1:0] ic_iret_reg; // From pic of pic.v
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wire ic_irq; // From pic of pic.v
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wire [LAW-1:0] ic_irq_addr; // From pic of pic.v
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wire [5:0] reg_addr;
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] data_in; // From p2e of packet2emesh.v
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wire [1:0] datamode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
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wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
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wire write_in; // From p2e of packet2emesh.v
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// End of automatics
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assign clkout = clk1;
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assign dut_active = 1'b1;
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assign wait_out = 1'b0;
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assign reg_write = write_in & access_in;
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assign reg_addr[5:0] = dstaddr_in[7:2];
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packet2emesh p2e (/*AUTOINST*/
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// Outputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[4:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]),
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// Inputs
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.packet_in (packet_in[PW-1:0]));
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pic #(.LAW(LAW),
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.IRQW(IRQW))
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pic (// Outputs
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.ic_flush (ic_flush),
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.ic_iret_reg (ic_iret_reg[LAW-1:0]),
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.ic_imask_reg (ic_imask_reg[IRQW-1:0]),
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.ic_ilat_reg (ic_ilat_reg[IRQW-1:0]),
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.ic_ipend_reg (ic_ipend_reg[IRQW-1:0]),
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.ic_irq (ic_irq),
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.ic_irq_addr (ic_irq_addr[LAW-1:0]),
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// Inputs
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.clk (clk1),
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.nreset (nreset),
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.reg_write (reg_write),
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.reg_addr (reg_addr[5:0]),
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.reg_wdata (data_in[31:0]),
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.ext_irq ({(IRQW){1'b0}}),
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.sq_pc_next_ra ({(LAW){1'b0}}),
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.de_rti_e1 (1'b0),
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.sq_global_irq_en (1'b1),
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.sq_ic_wait (1'b0));
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../emesh/hdl")
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// End:
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