oh/chip/eda/open

#CONTENT

• Various open source tools
• front end: yosys
• analog simulator: spice
• verilog simulator: iverilog, verilator
• pnr: n/a
• lvs: n/a
• drc: n/a
• schmatic entry: n/a
• polygon-push: n/a
• analog circuit generators: n/a
• logical equivalence : n/a
• dft compiler : n/a
• power compiler: n/a
• power grid analysis: n/a
• extraction tool: n/a
• signal integrity: n/a
• cell characterization: n/a
• transistor level STA: n/a
• signoff STA: n/a
• scan pattern generator: n/a
• memory compiler: n/a
• generic standard cell library: n/a
• generic io library: n/a