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26 lines
569 B
Markdown
26 lines
569 B
Markdown
#CONTENT
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* Various open source tools
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* front end: yosys
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* analog simulator: spice
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* verilog simulator: iverilog, verilator
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* pnr: n/a
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* lvs: n/a
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* drc: n/a
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* schmatic entry: n/a
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* polygon-push: n/a
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* analog circuit generators: n/a
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* logical equivalence : n/a
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* dft compiler : n/a
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* power compiler: n/a
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* power grid analysis: n/a
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* extraction tool: n/a
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* signal integrity: n/a
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* cell characterization: n/a
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* transistor level STA: n/a
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* signoff STA: n/a
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* scan pattern generator: n/a
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* memory compiler: n/a
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* generic standard cell library: n/a
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* generic io library: n/a
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