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- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
67 lines
1.6 KiB
Verilog
67 lines
1.6 KiB
Verilog
/*******************************************************************************
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* Function: EMESH Transaction Monitor
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* Author: Andreas Olofsson
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* License: MIT (see LICENSE file in OH! repository)
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*
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******************************************************************************/
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/* verilator lint_off STMTDLY */
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module emesh_monitor
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# (parameter PW = 104, // packet width
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parameter FILENAME = "UNDEFINED", // filename
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parameter ENABLE = 0 // enable block
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)
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(
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//clock and reset
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input clk,
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input nreset,
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//monitors transaction on the wire
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input dut_valid,
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input [PW-1:0] dut_packet,
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input ready_in
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);
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generate
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if(ENABLE)
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begin
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//core name for trace
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reg [31:0] ftrace;
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reg [255:0] tracefile;
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initial
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begin
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#10
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$sformat(tracefile,"%0s_%0h%s",FILENAME);
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ftrace = $fopen({tracefile}, "w");
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end
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always @ (posedge clk)
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if(nreset & dut_valid & ready_in)
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if (PW==112) begin: p112
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$fwrite(ftrace, "%h_%h_%h_%h\n",
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dut_packet[110:80],
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dut_packet[79:48],
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dut_packet[47:16],
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dut_packet[15:0]);
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end
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else if (PW==144) begin: p144
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$fwrite(ftrace, "%h_%h_%h_%h\n",
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dut_packet[143:112],
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dut_packet[111:48],
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dut_packet[47:16],
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dut_packet[15:0]);
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end
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else if (PW==208) begin: p208
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$fwrite(ftrace, "%h_%h_%h_%h_%h\n",
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dut_packet[207:144],
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dut_packet[143:112],
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dut_packet[111:48],
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dut_packet[47:16],
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dut_packet[15:0]);
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end
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end
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endgenerate
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endmodule // emesh_monitor
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