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152 lines
4.0 KiB
Verilog
152 lines
4.0 KiB
Verilog
/* verilator lint_off STMTDLY */
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module dv_driver #( parameter N = 1, // "N" packets wide
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parameter AW = 32, // address width
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parameter PW = 104, // packet width (derived)
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parameter IDW = 12, // id width
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parameter NAME = "none", // north, south etc
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parameter STIMS = 1, // number of stimulus
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parameter MAW = 16 // 64KB memory address width
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)
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(
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//control signals
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input clkin,
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input clkout,
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input nreset,
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input start, //starts test
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input [IDW-1:0] coreid, //everything has a coreid!
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//inputs for monitoring
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input [N-1:0] dut_access,
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input [N*PW-1:0] dut_packet,
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input [N-1:0] dut_wait,
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//stimulus to drive
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output [N-1:0] stim_access,
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output [N*PW-1:0] stim_packet,
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output [N-1:0] stim_wait,
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output stim_done
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);
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//#############
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//LOCAL WIRES
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//#############
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reg [IDW-1:0] offset;
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wire [N*32-1:0] stim_count;
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wire [N-1:0] stim_vec_done;
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wire [N*IDW-1:0] coreid_array;
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wire [N*PW-1:0] mem_packet_out;
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wire [N-1:0] mem_access_out;
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wire [N-1:0] mem_wait_out;
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/*AUTOWIRE*/
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//###########################################
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//STIMULUS
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//###########################################
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assign stim_done = &(stim_vec_done[N-1:0]);
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genvar i;
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generate
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for(i=0;i<N;i=i+1) begin : stim
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if(i<STIMS) begin
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stimulus #(.PW(PW),
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.INDEX(i),
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.NAME(NAME))
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stimulus (// Outputs
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.stim_access (stim_access[0]),
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.stim_packet (stim_packet[(i+1)*PW-1:i*PW]),
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.stim_count (stim_count[(i+1)*32-1:i*32]),
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.stim_done (stim_vec_done[i]),
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.stim_wait (stim_wait[i]),
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// Inputs
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.clk (clkin),
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.nreset (nreset),
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.start (start),
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.dut_wait (dut_wait[i])
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);
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end // if (i<STIMS)
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else
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begin
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assign stim_access[i] = 'b0;
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assign stim_packet[(i+1)*PW-1:i*PW] = 'b0;
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assign stim_count[(i+1)*32-1:i*32] = 'b0;
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assign stim_vec_done[i] = 'b1;
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assign stim_wait[i] = 'b0;
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end
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end // block: stim
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endgenerate
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//###########################################
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//MONITORS (USE CLK2)
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//###########################################
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//Increment coreID depending on counter and orientation of side block
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//TODO: parametrize
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initial
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begin
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if(NAME=="north" | NAME=="south" )
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offset=12'h001;
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else
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offset=12'h040;
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end
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genvar j;
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generate
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for(j=0;j<N;j=j+1) begin : mon
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assign coreid_array[(j+1)*IDW-1:j*IDW] = coreid[IDW-1:0] + j*offset;
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//MONITOR
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emesh_monitor #(.PW(PW),
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.NAME(NAME),
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.IDW(IDW)
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)
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monitor (//inputs
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.clk (clkout),
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.nreset (nreset),
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.dut_access (dut_access[j]),
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.dut_packet (dut_packet[(j+1)*PW-1:j*PW]),
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.coreid (coreid_array[(j+1)*IDW-1:j*IDW]),
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.wait_in (stim_wait[j])
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);
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end // for (i=0;i<N;i=i+1)
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endgenerate
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//###########################################
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//MEMORY
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//###########################################
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genvar k;
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generate
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for(j=0;j<N;j=j+1) begin : mem
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ememory #(.NAME(NAME),
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.IDW(IDW),
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.PW(PW),
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.AW(AW)
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)
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ememory(// Outputs
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.wait_out (mem_wait_out[j]),
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.access_out (mem_access_out[j]),
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.packet_out (mem_packet_out[(j+1)*PW-1:j*PW]),
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// Inputs
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.clk (clkout),
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.nreset (nreset),
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.coreid (coreid[IDW-1:0]),
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.access_in (dut_access[j]),
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.packet_in (dut_packet[(j+1)*PW-1:j*PW]),
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.wait_in (dut_wait[j])
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);
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end
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endgenerate
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//###########################################
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//MUX BETWEEN STIMULUS AND MEMORY
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//###########################################
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//stimulus has higher priority
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//TODO: Implement
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endmodule // dv_driver
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl")
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// End:
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