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https://github.com/aolofsson/oh.git
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19fa611bb9
- adding more chip code - pushing memory stuff into common - making common "oh_" naming class -
67 lines
2.0 KiB
Verilog
67 lines
2.0 KiB
Verilog
// ###############################################################
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// # FUNCTION: Synchronous clock divider that divides by integer
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// ###############################################################
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module oh_clockdiv(/*AUTOARG*/
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// Outputs
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clkout,
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// Inputs
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clkin, divcfg, reset
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);
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input clkin; // Input clock
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input [3:0] divcfg; // Divide factor (1-128)
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input reset; // Counter init
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output clkout; // Divided clock phase aligned with clkin
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reg clkout_reg;
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reg [7:0] counter;
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reg [7:0] divcfg_dec;
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reg [3:0] divcfg_reg;
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wire div_bp;
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wire posedge_match;
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wire negedge_match;
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// ###################
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// # Decode divcfg
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// ###################
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always @ (divcfg[3:0])
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casez (divcfg[3:0])
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4'b0001 : divcfg_dec[7:0] = 8'b00000010; // Divide by 2
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4'b0010 : divcfg_dec[7:0] = 8'b00000100; // Divide by 4
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4'b0011 : divcfg_dec[7:0] = 8'b00001000; // Divide by 8
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4'b0100 : divcfg_dec[7:0] = 8'b00010000; // Divide by 16
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4'b0101 : divcfg_dec[7:0] = 8'b00100000; // Divide by 32
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4'b0110 : divcfg_dec[7:0] = 8'b01000000; // Divide by 64
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4'b0111 : divcfg_dec[7:0] = 8'b10000000; // Divide by 128
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default : divcfg_dec[7:0] = 8'b00000000; // others
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endcase
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always @ (posedge clkin or posedge reset)
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if(reset)
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counter[7:0] <= 8'b00000001;
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else if(posedge_match)
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counter[7:0] <= 8'b00000001;// Self resetting
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else
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counter[7:0] <= (counter[7:0] + 8'b00000001);
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assign posedge_match = (counter[7:0]==divcfg_dec[7:0]);
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assign negedge_match = (counter[7:0]=={1'b0,divcfg_dec[7:1]});
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always @ (posedge clkin or posedge reset)
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if(reset)
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clkout_reg <= 1'b0;
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else if(posedge_match)
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clkout_reg <= 1'b1;
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else if(negedge_match)
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clkout_reg <= 1'b0;
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//Divide by one bypass
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assign div_bp = (divcfg[3:0]==4'b0000);
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assign clkout = div_bp ? clkin : clkout_reg;
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endmodule // oh_clockdiv
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