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21 lines
273 B
Verilog
21 lines
273 B
Verilog
module oh_csa32 (/*AUTOARG*/
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// Outputs
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c, s,
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// Inputs
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in0, in1, in2
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);
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input in0;
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input in1;
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input in2;
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output c;
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output s;
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assign s = in0 ^ in1 ^ in2;
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assign c = (in0 & in1) | ( in1 & in2) | ( in2 & in0 );
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endmodule // oh_csa32
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