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36 lines
703 B
Verilog
36 lines
703 B
Verilog
//CSA6:2 Compressor
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module oh_csa62 (/*AUTOARG*/
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// Outputs
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s, c, cout0, cout1, cout2,
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// Inputs
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in0, in1, in2, in3, in4, in5, cin0, cin1, cin2
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);
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input in0;
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input in1;
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input in2;
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input in3;
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input in4;
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input in5;
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input cin0;
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input cin1;
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input cin2;
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output s;
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output c;
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output cout0;
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output cout1;
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output cout2;
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wire s_int0;
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wire s_int1;
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oh_csa32 csa32_0 (.in0(in0),.in1(in1),.in2(in2),.c(cout0),.s(s_int0));
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oh_csa32 csa32_1 (.in0(in3),.in1(in4),.in2(in5),.c(cout1),.s(s_int1));
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oh_csa42 csa42 (.in0(s_int0),.in1(s_int1),.in2(cin0),.in3(cin1),.cin(cin2),
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.cout(cout2),.c(c),.s(s));
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endmodule // oh_csa62
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