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19fa611bb9
- adding more chip code - pushing memory stuff into common - making common "oh_" naming class -
59 lines
1.2 KiB
V
59 lines
1.2 KiB
V
module oh_mux12(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in11, in10, in9, in8, in7, in6, in5, in4, in3, in2, in1, in0,
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sel11, sel10, sel9, sel8, sel7, sel6, sel5, sel4, sel3, sel2, sel1,
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sel0
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);
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parameter DW=99;
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//data inputs
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input [DW-1:0] in11;
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input [DW-1:0] in10;
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input [DW-1:0] in9;
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input [DW-1:0] in8;
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input [DW-1:0] in7;
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input [DW-1:0] in6;
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input [DW-1:0] in5;
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input [DW-1:0] in4;
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input [DW-1:0] in3;
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input [DW-1:0] in2;
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input [DW-1:0] in1;
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input [DW-1:0] in0;
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//select inputs
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input sel11;
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input sel10;
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input sel9;
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input sel8;
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input sel7;
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input sel6;
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input sel5;
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input sel4;
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input sel3;
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input sel2;
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input sel1;
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input sel0;
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output [DW-1:0] out;
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assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
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{(DW){sel1}} & in1[DW-1:0] |
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{(DW){sel2}} & in2[DW-1:0] |
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{(DW){sel3}} & in3[DW-1:0] |
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{(DW){sel4}} & in4[DW-1:0] |
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{(DW){sel5}} & in5[DW-1:0] |
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{(DW){sel6}} & in6[DW-1:0] |
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{(DW){sel7}} & in7[DW-1:0] |
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{(DW){sel8}} & in8[DW-1:0] |
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{(DW){sel9}} & in9[DW-1:0] |
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{(DW){sel10}} & in10[DW-1:0] |
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{(DW){sel11}} & in11[DW-1:0]);
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endmodule // oh_mux12
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