mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-17 20:02:53 +08:00
24 lines
347 B
Verilog
24 lines
347 B
Verilog
|
|
module IBUF (O, I);
|
|
|
|
parameter CAPACITANCE = "DONT_CARE";
|
|
parameter IBUF_DELAY_VALUE = "0";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IFD_DELAY_VALUE = "AUTO";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
|
|
`ifdef XIL_TIMING
|
|
|
|
parameter LOC = " UNPLACED";
|
|
|
|
`endif
|
|
|
|
|
|
output O;
|
|
input I;
|
|
|
|
buf B1 (O, I);
|
|
|
|
endmodule
|
|
|