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27 lines
329 B
Verilog
27 lines
329 B
Verilog
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module IBUFDS_GTE2 (
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O,
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ODIV2,
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CEB,
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I,
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IB
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);
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`ifdef XIL_TIMING
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parameter LOC = "UNPLACED";
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`endif
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parameter CLKCM_CFG = "TRUE";
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parameter CLKRCV_TRST = "TRUE";
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parameter [1:0] CLKSWING_CFG = 2'b11;
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output O;
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output ODIV2;
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input CEB;
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input I;
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input IB;
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endmodule
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