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14 lines
222 B
Verilog
14 lines
222 B
Verilog
odule OBUFTDS_DCIEN (O, OB, DCITERMDISABLE, I, T);
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parameter IOSTANDARD = "DEFAULT";
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parameter SLEW = "SLOW";
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output O;
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output OB;
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input DCITERMDISABLE;
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input I;
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input T;
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endmodule
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