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ba32323306
-moving to "real" Xilinx PLL instantiation -one PLL for CCLK one for LCLK -removing clock dividers, can't work at speed, put inside model -configuration needs to be done differently -removing pll_bypass signal, can't work with logic -clocks should be done with hard macro primitives (no logic)
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OH!
Open Hardware (Pure and Simple)
(work in progress...)