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https://github.com/aolofsson/oh.git
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376 lines
13 KiB
Verilog
376 lines
13 KiB
Verilog
/*
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########################################################################
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EPIPHANY CONFIGURATION REGISTER (32bit access)
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########################################################################
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-------------------------------------------------------------
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ESYSRESET ***Elink reset***
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[0] 0 - elink active
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1 - elink in reset
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-------------------------------------------------------------
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ESYSTX ***Elink transmitter configuration***
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[0] 0 - link TX disable
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1 - link TX enable
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[1] 0 - normal pass through transaction mode
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1 - mmu mode
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[3:2] 00 - normal mode
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01 - gpio drive mode
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10 - reserved
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11 - reserved
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[7:4] Transmit control mode for eMesh
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[11:8] 0000 - No division, full speed
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0001 - Divide by 2
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[12] Bypass mode (clkin used for tx_lclk)
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[13] AXI slave read timeout enable
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-------------------------------------------------------------
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ESYSRX ***Elink receiver configuration***
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[0] 0 - link RX disable
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1 - link RX enable
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[1] 0 - normal transaction mode
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1 - mmu mode
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[3:2] 00 - normal mode
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01 - gpio sample mode (drive rd wait pins from registers)
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10 - reserved
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11 - reserved
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-------------------------------------------------------------
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ESYSCLK ***Epiphany clock frequency setting***
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[3:0] Output divider
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0000 - Clock turned off
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0001 - CLKIN/64
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0010 - CLKIN/32
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0011 - CLKIN/16
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0100 - CLKIN/8
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0101 - CLKIN/4
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0110 - CLKIN/2
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0111 - CLKIN/1 (full speed)
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1XXX - RESERVED
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[7:4] PLL settings (TBD)
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[8] PLL bypass mode (cclk is set to clkin)
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-------------------------------------------------------------
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ESYSCOREID ***CORE ID***
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[5:0] Column ID-->default at powerup/reset
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[11:6] Row ID
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-------------------------------------------------------------
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ESYSLATFORM ***Platform ID (read only)***
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[7:0] Platform model number
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-------------------------------------------------------------
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ESYSDATAIN ***Data on elink input pins
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[7:0] rx_data[7:0]
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[8] tx_frame
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[9] tx_wait_rd
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[10] tx_wait_wr
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-------------------------------------------------------------
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ESYSDATAOUT ***Data on eLink output pins
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[7:0] tx_data[7:0]
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[8] tx_frame
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[9] rx_wait_rd
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[10] rx_wait_wr
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-------------------------------------------------------------
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ESYSDEBUG ***Various debug signals from elink
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[31] embox_not_empty
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//RX signals
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[30] emesh_rx_rd_wait
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[29] emesh_rx_wr_wait
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[28] esaxi_emrr_rd_en
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[27] emrr_full
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[26] emrr_progfull
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[25] emrr_wr_en
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[24] emaxi_emrq_rd_en
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[23] emrq_progfull
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[22] emrq_wr_en
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[21] emaxi_emwr_rd_en
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[20] emwr_progfull
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[19] emwr_wr_en (rx)
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//TX signals
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[18] e_tx_rd_wait
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[17] e_tx_wr_wait
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[16] emrr_rd_en
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[15] emaxi_emrr_prog_full
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[14] emaxi_emrr_wr_en
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[13] emrq_rd_en
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[12 esaxi_emrq_prog_full
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[11] esaxi_emrq_wr_en
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[10] emwr_rd_en
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[9] esaxi_emwr_prog_full
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[8] esaxi_emwr_wr_en
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//Sticky signals
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[7] reserved
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[6] emrr_full (rx)
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[5] emrq_full (rx)
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[4] emwr_full (rx)
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[3] emaxi_emrr_full (tx)
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[2] esaxi_emrq_full (tx)
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[1] esaxi_emwr_full (tx)
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[0] embox_full (mailbox)
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########################################################################
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*/
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module ecfg (/*AUTOARG*/
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// Outputs
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mi_dout, ecfg_reset, ecfg_resetb, ecfg_tx_enable,
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ecfg_tx_mmu_enable, ecfg_tx_gpio_enable, ecfg_tx_ctrlmode,
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ecfg_tx_clkdiv, ecfg_tx_clkbypass, ecfg_axi_timeout_enable,
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ecfg_rx_enable, ecfg_rx_mmu_enable, ecfg_rx_gpio_enable,
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ecfg_cclk_en, ecfg_cclk_div, ecfg_cclk_pllcfg, ecfg_cclk_bypass,
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ecfg_coreid, ecfg_dataout, embox_not_empty, embox_full,
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// Inputs
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hw_reset, clk, mi_en, mi_we, mi_addr, mi_din, ecfg_rx_datain,
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ecfg_tx_datain, ecfg_tx_debug, ecfg_rx_debug
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);
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/******************************/
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/*Compile Time Parameters */
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/******************************/
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parameter RFAW = 5; //32 registers for now
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parameter DEFAULT_COREID = 12'h808; //reset value for ecfg_coreid
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parameter DEFAULT_VERSION = 16'h0000; //reset value for version
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/******************************/
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/*HARDWARE RESET (POR/BUTTON) */
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/******************************/
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input hw_reset;
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/*****************************/
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/*SIMPLE MEMORY INTERFACE */
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/*****************************/
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input clk;
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input mi_en;
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input mi_we; //single we, must write 32 bit words
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input [19:0] mi_addr; //complete physical address (no shifting!)
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input [31:0] mi_din;
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output [31:0] mi_dout;
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/*****************************/
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/*ELINK CONTROL SIGNALS */
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/*****************************/
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//reset
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output ecfg_reset; //reset for all elink logic
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output ecfg_resetb; //reset for epiphany (active low)
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//tx
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output ecfg_tx_enable; //enable signal for TX
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output ecfg_tx_mmu_enable; //enables MMU on transmit path
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output ecfg_tx_gpio_enable; //forces TX output pins to constants
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output [3:0] ecfg_tx_ctrlmode; //value for emesh ctrlmode tag
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output [3:0] ecfg_tx_clkdiv; //transmit clock divider
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output ecfg_tx_clkbypass; //transmit clock bypass
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output ecfg_axi_timeout_enable;//enables axi-slave timeout circuit
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//rx
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output ecfg_rx_enable; //enable signal for rx
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output ecfg_rx_mmu_enable; //enables MMU on rx path
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output ecfg_rx_gpio_enable; //forces rx wait pins to constants
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//cclk
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output ecfg_cclk_en; //cclk enable
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output [3:0] ecfg_cclk_div; //cclk divider setting
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output [3:0] ecfg_cclk_pllcfg; //pll configuration
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output ecfg_cclk_bypass; //pll bypass
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//coreid
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output [11:0] ecfg_coreid; //core-id of fpga elink
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//gpio
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input [8:0] ecfg_rx_datain; //frame and data
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input [1:0] ecfg_tx_datain; //wait signals
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output [10:0] ecfg_dataout; //data for elink outputs
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//debug
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output embox_not_empty; //not-empty
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output embox_full; //full
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input [15:0] ecfg_tx_debug; //etx debug signals
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input [15:0] ecfg_rx_debug; //etx debug signals
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/*------------------------BODY CODE---------------------------------------*/
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//registers
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reg ecfg_reset_reg;
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reg [13:0] ecfg_cfgtx_reg;
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reg [4:0] ecfg_cfgrx_reg;
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reg [8:0] ecfg_cfgclk_reg;
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reg [11:0] ecfg_coreid_reg;
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reg [15:0] ecfg_version_reg;
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reg [10:0] ecfg_datain_reg;
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reg [10:0] ecfg_dataout_reg;
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reg [7:0] ecfg_debug_reg;
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reg [31:0] mi_dout;
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//wires
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wire ecfg_read;
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wire ecfg_write;
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wire ecfg_match;
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wire ecfg_regmux;
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wire [31:0] ecfg_reg_mux;
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wire ecfg_cfgtx_write;
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wire ecfg_cfgrx_write;
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wire ecfg_cfgclk_write;
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wire ecfg_coreid_write;
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wire ecfg_version_write;
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wire ecfg_dataout_write;
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wire ecfg_reset_write;
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wire [31:0] ecfg_debug_vector;
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/*****************************/
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/*ADDRESS DECODE LOGIC */
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/*****************************/
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//read/write decode
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assign ecfg_write = mi_en & mi_we;
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assign ecfg_read = mi_en & ~mi_we;
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//Config write enables
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assign ecfg_reset_write = ecfg_write & (mi_addr[RFAW+1:2]==`ESYSRESET);
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assign ecfg_cfgtx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ESYSTX);
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assign ecfg_cfgrx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ESYSRX);
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assign ecfg_cfgclk_write = ecfg_write & (mi_addr[RFAW+1:2]==`ESYSCLK);
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assign ecfg_coreid_write = ecfg_write & (mi_addr[RFAW+1:2]==`ESYSCOREID);
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assign ecfg_dataout_write = ecfg_write & (mi_addr[RFAW+1:2]==`ESYSDATAOUT);
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//###########################
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//# ESYSRESET
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//###########################
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always @ (posedge clk)
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if(hw_reset)
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ecfg_reset_reg <= 1'b0;
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else if (ecfg_reset_write)
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ecfg_reset_reg <= mi_din[0];
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assign ecfg_reset = ecfg_reset_reg | hw_reset;
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assign ecfg_resetb = ~ecfg_reset;
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//###########################
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//# ESYSTX
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//###########################
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always @ (posedge clk)
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if(hw_reset)
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ecfg_cfgtx_reg[13:0] <= 14'b0;
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else if (ecfg_cfgtx_write)
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ecfg_cfgtx_reg[13:0] <= mi_din[13:0];
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assign ecfg_tx_enable = ecfg_cfgtx_reg[0];
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assign ecfg_tx_mmu_enable = ecfg_cfgtx_reg[1];
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assign ecfg_tx_gpio_enable = (ecfg_cfgtx_reg[3:2]==2'b01);
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assign ecfg_tx_ctrlmode[3:0] = ecfg_cfgtx_reg[7:4];
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assign ecfg_tx_clkdiv[3:0] = ecfg_cfgtx_reg[11:8];
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assign ecfg_tx_clkbypass = ecfg_cfgtx_reg[12];
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assign ecfg_axi_timeout_enable = ecfg_cfgtx_reg[13];
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//###########################
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//# ESYSRX
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//###########################
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always @ (posedge clk)
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if(hw_reset)
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ecfg_cfgrx_reg[4:0] <= 5'b0;
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else if (ecfg_cfgrx_write)
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ecfg_cfgrx_reg[4:0] <= mi_din[4:0];
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assign ecfg_rx_enable = ecfg_cfgrx_reg[0];
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assign ecfg_rx_mmu_enable = ecfg_cfgrx_reg[1];
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assign ecfg_rx_gpio_enable = ecfg_cfgrx_reg[3:2]==2'b01;
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//###########################
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//# ESYSCLK
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//###########################
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always @ (posedge clk)
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if(hw_reset)
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ecfg_cfgclk_reg[8:0] <= 9'b0;
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else if (ecfg_cfgclk_write)
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ecfg_cfgclk_reg[8:0] <= mi_din[8:0];
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assign ecfg_cclk_en = ~(ecfg_cfgclk_reg[3:0]==4'b0000);
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assign ecfg_cclk_div[3:0] = ecfg_cfgclk_reg[3:0];
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assign ecfg_cclk_pllcfg[3:0] = ecfg_cfgclk_reg[7:4];
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assign ecfg_cclk_bypass = ecfg_cfgclk_reg[8];
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//###########################
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//# ESYSCOREID
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//###########################
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always @ (posedge clk)
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if(hw_reset)
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ecfg_coreid_reg[11:0] <= DEFAULT_COREID;
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else if (ecfg_coreid_write)
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ecfg_coreid_reg[11:0] <= mi_din[11:0];
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assign ecfg_coreid[11:0] = ecfg_coreid_reg[11:0];
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//###########################
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//# ESYSVERSION
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//###########################
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always @ (posedge clk)
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if(hw_reset)
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ecfg_version_reg[7:0] <= DEFAULT_VERSION;
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else if (ecfg_version_write)
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ecfg_version_reg[7:0] <= mi_din[7:0];
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//###########################
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//# ESYSDATAIN
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//###########################
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always @ (posedge clk)
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ecfg_datain_reg[10:0] <= {ecfg_rx_datain[1:0], ecfg_rx_datain[8:0]};
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//###########################
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//# ESYSDATAOUT
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//###########################
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always @ (posedge clk)
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if(hw_reset)
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ecfg_dataout_reg[10:0] <= 11'd0;
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else if (ecfg_dataout_write)
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ecfg_dataout_reg[10:0] <= mi_din[10:0];
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assign ecfg_dataout[10:0] = ecfg_dataout_reg[10:0];
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//###########################
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//# ESYSDEBUG
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//###########################
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assign ecfg_debug_vector[31:0]= {//other debug signals
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embox_not_empty,
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ecfg_rx_debug[15:3],
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ecfg_tx_debug[15:3],
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//sticky signals
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ecfg_rx_debug[2:0],
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ecfg_tx_debug[2:0],
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embox_full
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};
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always @ (posedge clk)
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if(hw_reset)
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ecfg_debug_reg[7:0] <= 8'd0;
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else
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ecfg_debug_reg[7:0] <=ecfg_debug_reg[7:0] | ecfg_debug_vector[7:0];
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//###############################
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//# DATA READBACK MUX
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//###############################
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//Pipelineing readback
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always @ (posedge clk)
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if(ecfg_read)
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case(mi_addr[RFAW+1:2])
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`ESYSRESET: mi_dout[31:0] <= {31'b0, ecfg_reset_reg};
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`ESYSTX: mi_dout[31:0] <= {19'b0, ecfg_cfgtx_reg[12:0]};
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`ESYSRX: mi_dout[31:0] <= {27'b0, ecfg_cfgrx_reg[4:0]};
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`ESYSCLK: mi_dout[31:0] <= {24'b0, ecfg_cfgclk_reg[7:0]};
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`ESYSCOREID: mi_dout[31:0] <= {20'b0, ecfg_coreid_reg[11:0]};
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`ESYSVERSION: mi_dout[31:0] <= {24'b0, ecfg_version_reg[7:0]};
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`ESYSDATAIN: mi_dout[31:0] <= {21'b0, ecfg_datain_reg[10:0]};
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`ESYSDATAOUT: mi_dout[31:0] <= {21'b0, ecfg_dataout_reg[10:0]};
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`ESYSDEBUG: mi_dout[31:0] <= {ecfg_debug_vector[31:8],ecfg_debug_reg[7:0]};
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default: mi_dout[31:0] <= 32'd0;
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endcase
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endmodule // ecfg
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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