FPGA/oh

mirror of https://github.com/aolofsson/oh.git synced 2025-01-30 02:32:53 +08:00

History

Andreas Olofsson bb4a602f7f New "dut files"

- new clocks (clk1 and 2)
- simpler names
- fifo dut

2016-02-24 14:19:57 -05:00

tests

New "dut files"

2016-02-24 14:19:57 -05:00

build_all.sh

Adding testbench for clockdiv and gray converter

2016-02-23 17:17:41 -05:00

build.sh

Adding testbench for clockdiv and gray converter

2016-02-23 17:17:41 -05:00

cfg_random.v

New "dut files"

2016-02-24 14:19:57 -05:00

dut_clockdiv.v

New "dut files"

2016-02-24 14:19:57 -05:00

dut_debouncer.v

New "dut files"

2016-02-24 14:19:57 -05:00

dut_fifo_generic.v

New "dut files"

2016-02-24 14:19:57 -05:00

dut_gray.v

New "dut files"

2016-02-24 14:19:57 -05:00

dut_oh_clockdiv.v

Adding testbench for clockdiv and gray converter

2016-02-23 17:17:41 -05:00

dut_oh_debouncer.v

Adding debouncer circuit

2016-02-23 15:41:18 -05:00

dut_oh_gray.v

Adding testbench for clockdiv and gray converter

2016-02-23 17:17:41 -05:00

dut.v

Making AW main parameter

2016-01-11 15:05:21 -05:00

dv_ctrl.v

Changing timeout

2016-01-13 15:32:15 -05:00

dv_driver.v

Interface cleanup

2016-01-19 13:33:08 -05:00

dv_random.v

Moving to MIT license

2015-11-06 11:25:05 -05:00

dv_top.v

Changing timeout

2016-01-13 15:32:15 -05:00

libs.cmd

Adding testbench for clockdiv and gray converter

2016-02-23 17:17:41 -05:00

README.md

New "dut files"

2016-02-24 14:19:57 -05:00

run.sh

Adding clk90 output to clkdiv

2016-02-23 17:49:08 -05:00

stimulus.v

Changing emesh stimulus suffix ti "*.emf"

2016-01-10 11:57:38 -05:00

timescale.v

Adding missing files

2015-11-03 14:16:50 -05:00

README.md

What defines are used

iverilog -g2005 -DTARGET_SIM=1 $cfg $core.v $DV -f $LIBS -o $core.bin

How to compile all duts?

The script "build_all.sh" builds all dut files in this directory with random

./build_all.sh