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bc6641bcd0
- Divide and conquer, use the par2ser wait signal to hold off on read - Removed the stupid byte done state! Was too complicated.
217 lines
7.7 KiB
Verilog
217 lines
7.7 KiB
Verilog
//#############################################################################
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//# Purpose: SPI slave IO and statemachine #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see below) #
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//#############################################################################
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module spi_master_io(/*AUTOARG*/
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// Outputs
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spi_state, fifo_read, rx_data, rx_access, sclk, mosi, ss,
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// Inputs
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clk, nreset, spi_en, cpol, cpha, lsbfirst, clkdiv_reg, cmd_reg,
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emode, fifo_dout, fifo_empty, miso
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);
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//#################################
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//# INTERFACE
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//#################################
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//parameters
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parameter REGS = 16; // total regs (16/32/64)
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parameter AW = 32; // address width
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localparam PW = (2*AW+40); // packet width
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//clk, reset, cfg
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input clk; // core clock
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input nreset; // async active low reset
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//cfg
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input spi_en; // spi enable
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input cpol; // cpol
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input cpha; // cpha
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input lsbfirst; // send lsbfirst
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input [7:0] clkdiv_reg; // baudrate
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input [7:0] cmd_reg;
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input emode;
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output [1:0] spi_state; // current spi tx state
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//data to transmit
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input [7:0] fifo_dout; // data payload
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input fifo_empty; //
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output fifo_read; // read new byte
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//receive data (for sregs)
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output [63:0] rx_data; // rx data
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output rx_access; // transfer done
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//IO interface
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output sclk; // spi clock
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output mosi; // slave input
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output ss; // slave select
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input miso; // slave output
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reg [1:0] spi_state;
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reg fifo_empty_reg;
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reg load_byte;
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wire [7:0] data_out;
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wire [15:0] clkphase0;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire clkfall1; // From oh_clockdiv of oh_clockdiv.v
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wire clkout1; // From oh_clockdiv of oh_clockdiv.v
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wire clkrise1; // From oh_clockdiv of oh_clockdiv.v
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// End of automatics
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//#################################
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//# CLOCK GENERATOR
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//#################################
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assign clkphase0[7:0] = 'b0;
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assign clkphase0[15:8] = (clkdiv_reg[7:0]+1'b1)>>1;
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oh_clockdiv #(.DW(8))
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oh_clockdiv (.clkdiv (clkdiv_reg[7:0]),
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.clken (1'b1),
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.clkrise0 (period_match),
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.clkfall0 (phase_match),
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.clkphase1 (16'b0),
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.clkout0 (clkout),
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/*AUTOINST*/
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// Outputs
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.clkout1 (clkout1),
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.clkrise1 (clkrise1),
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.clkfall1 (clkfall1),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.clkphase0 (clkphase0[15:0]));
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//#################################
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//# STATE MACHINE
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//#################################
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`define SPI_IDLE 2'b00 // set ss to 1
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`define SPI_SETUP 2'b01 // setup time
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`define SPI_DATA 2'b10 // send data
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`define SPI_HOLD 2'b11 // hold time
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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spi_state[1:0] <= `SPI_IDLE;
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else
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case (spi_state[1:0])
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`SPI_IDLE :
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spi_state[1:0] <= fifo_read ? `SPI_SETUP : `SPI_IDLE;
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`SPI_SETUP :
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spi_state[1:0] <= period_match ? `SPI_DATA : `SPI_SETUP;
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`SPI_DATA :
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spi_state[1:0] <= data_done ? `SPI_HOLD : `SPI_DATA;
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`SPI_HOLD :
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spi_state[1:0] <= period_match ? `SPI_IDLE : `SPI_HOLD;
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endcase // case (spi_state[1:0])
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//read fifo on phase match (due to one cycle pipeline latency
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assign fifo_read = ~fifo_empty & ~spi_wait & period_match;
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//data done whne
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assign data_done = fifo_empty & ~spi_wait & period_match;
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//shift on every clock cycle while in datamode
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assign shift = period_match & (spi_state[1:0]==`SPI_DATA);
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//load is the result of the fifo_read
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always @ (posedge clk)
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load_byte <= fifo_read;
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//#################################
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//# CHIP SELECT
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//#################################
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assign ss = (spi_state[1:0]==`SPI_IDLE);
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//#################################
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//# DRIVE OUTPUT CLOCK
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//#################################
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assign sclk = clkout & (spi_state[1:0]==`SPI_DATA);
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//#################################
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//# TX SHIFT REGISTER
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//#################################
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assign data_out[7:0] = (emode & spi_state[1:0]==`SPI_IDLE) ? cmd_reg[7:0] :
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fifo_dout[7:0];
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oh_par2ser #(.PW(8),
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.SW(1))
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par2ser (// Outputs
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.dout (mosi), // serial output
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.access_out (),
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.wait_out (spi_wait),
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// Inputs
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.clk (clk),
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.nreset (nreset), // async active low reset
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.din (data_out[7:0] ), // 8 bit data from fifo
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.shift (shift), // shift on neg edge
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.datasize (8'd7), // 8 bits
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.load (load_byte), // load data from fifo
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.lsbfirst (lsbfirst), // serializer direction
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.fill (1'b0), // fill with slave data
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.wait_in (1'b0) // no wait
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);
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//#################################
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//# RX SHIFT REGISTER
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//#################################
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//generate access pulse at rise of ss
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oh_rise2pulse
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pulse (.out (rx_access),
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.clk (clk),
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.in (ss));
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oh_ser2par #(.PW(64),
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.SW(1))
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ser2par (//output
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.dout (rx_data[63:0]), // parallel data out
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//inputs
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.din (miso), // serial data in
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.clk (clk), // shift clk
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.lsbfirst (lsbfirst), // shift direction
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.shift (shift)); // shift data
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endmodule // spi_slave_io
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl" "../../emesh/hdl")
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// End:
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///////////////////////////////////////////////////////////////////////////////
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// The MIT License (MIT) //
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// //
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// Copyright (c) 2015-2016, Adapteva, Inc. //
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// //
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// Permission is hereby granted, free of charge, to any person obtaining a //
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// copy of this software and associated documentation files (the "Software") //
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// to deal in the Software without restriction, including without limitation //
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// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
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// and/or sell copies of the Software, and to permit persons to whom the //
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// Software is furnished to do so, subject to the following conditions: //
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// //
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// The above copyright notice and this permission notice shall be included //
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// in all copies or substantial portions of the Software. //
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// //
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
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// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
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// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
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// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
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// //
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///////////////////////////////////////////////////////////////////////////////
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