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15 lines
487 B
Systemverilog
15 lines
487 B
Systemverilog
//8 bit registers [5:0]
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`ifndef SPI_REGMAP_VH_
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`define SPI_REGMAP_VH_
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`define SPI_CONFIG 6'd0 // config register
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`define SPI_STATUS 6'd1 // status register
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`define SPI_CLKDIV 6'd2 // baud rate (master)
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`define SPI_CMD 6'd3 // manual ss control (master)
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`define SPI_TX 6'd8 // TX FIFO/RETURN DATA (8)
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`define SPI_RX0 6'd16 // RX
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`define SPI_RX1 6'd20 // RX upper
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`define SPI_USER 6'd32 // user regs (slave)
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`endif // `ifndef SPI_REGMAP_VH_
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