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9e9d323025
-Should be ifdef, since this is a global. You will never be doing and not an asic at the same time!
41 lines
1.1 KiB
Verilog
41 lines
1.1 KiB
Verilog
//#############################################################################
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//# Function: Clock 'OR' gate #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_clockor #(parameter N = 1) // number of clock inputs
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(
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input [N-1:0] clkin,// one hot clock inputs (only one is active!)
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output clkout
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);
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`ifdef CFG_ASIC
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generate
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if((N==4))
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begin : asic
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asic_clockor4 ior (/*AUTOINST*/
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// Outputs
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.clkout (clkout),
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// Inputs
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.clkin (clkin[3:0]));
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end // block: g0
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else if((N==2))
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begin : asic
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asic_clockor2 ior (/*AUTOINST*/
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// Outputs
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.clkout (clkout),
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// Inputs
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.clkin (clkin[1:0]));
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end
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endgenerate
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`else
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assign clkout = |(clkin[N-1:0]);
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`endif
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endmodule // oh_clockmux
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