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6d1735d3b9
-Better to fix to avoid issues across different synthesis platform (even if standard would allow if for verilog2005)
35 lines
1.0 KiB
Verilog
35 lines
1.0 KiB
Verilog
//#############################################################################
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//# Function: Delays input signal by N clock cycles #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_delay #(parameter DW = 1, // width of data
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parameter N = 1 // clock cycle delay by
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)
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(
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input [DW-1:0] in, // input
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input clk,//clock input
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output [DW-1:0] out // output
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);
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reg [DW-1:0] sync_pipe[N-1:0];
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genvar i;
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generate
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always @ (posedge clk)
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sync_pipe[0]<=in[DW-1:0];
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for(i=1;i<N;i=i+1) begin: gen_pipe
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always @ (posedge clk)
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sync_pipe[i]<=sync_pipe[i-1];
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end
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endgenerate
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assign out[DW-1:0] = sync_pipe[N-1];
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endmodule // oh_delay
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