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6d1735d3b9
-Better to fix to avoid issues across different synthesis platform (even if standard would allow if for verilog2005)
89 lines
2.9 KiB
Verilog
89 lines
2.9 KiB
Verilog
//#############################################################################
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//# Purpose: Low power standby state machine #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_standby #(parameter PD = 5,// cycles to stay awake after "wakeup"
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parameter N = 5)// cycles delay of irq_reset after posedge
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(//inputs
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input clkin, //clock input
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input nreset,//async active low reset
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input testenable,//disable standby (static signal)
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input wakeup, //wake up (level, active high)
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input idle, //idle indicator
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//outputs
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output resetout,//synchronous one clock reset pulse
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output clkout //clock output
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);
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//Wire declarations
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reg [PD-1:0] wakeup_pipe;
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wire sync_reset;
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wire sync_reset_pulse;
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wire wakeup_now;
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wire clk_en;
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//####################################################################
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// -Creating an edge one clock cycle pulse on rising edge of reset
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// -Event can be used to boot a CPU and any other master as an example
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// -Given the clock dependancies, it was deemed safest to put this
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// function here
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//####################################################################
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// Synchronizing reset to clock to avoid metastability
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oh_dsync #(.PS(2)) oh_dsync (//outputs
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.dout(sync_reset),
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//inputs
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.din(nreset),
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.clk(clkin)
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);
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// Detecting rising edge of delayed reset
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oh_edge2pulse oh_e2p (//outputs
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.out (sync_reset_pulse),
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//inputs
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.clk (clkin),
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.nreset (nreset),
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.in (sync_reset));
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// Delay irq event by N clock cycles
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oh_delay #(.N(N)) oh_delay (//outputs
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.out (resetout),
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//inputs
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.in (sync_reset_pulse),
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.clk (clkin));
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//####################################################################
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// Clock gating circuit for output clock
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// EVent can be used to boot a CPU andcany other master as an example
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//####################################################################
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//Adding reset to wakeup signal
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assign wakeup_now = sync_reset_pulse | wakeup;
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// Stay awake for PD cycles
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always @ (posedge clkin or negedge nreset)
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if(!nreset)
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wakeup_pipe[PD-1:0] <= 'b0;
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else
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wakeup_pipe[PD-1:0] <= {wakeup_pipe[PD-2:0], wakeup_now};
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// Clock enable
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assign clk_en = wakeup | //immediate wakeup
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(|wakeup_pipe[PD-1:0]) | //anything in pipe
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~idle; //core not in idle
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// Clock gating cell
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oh_clockgate oh_clockgate (.eclk(clkout),
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.clk(clkin),
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.en(clk_en),
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.te(testenable));
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endmodule // oh_standby
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