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32 lines
1.1 KiB
Verilog
32 lines
1.1 KiB
Verilog
//#############################################################################
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//# Purpose: Stretches a pulse by DW+1 clock cycles #
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//# Adds one cycle latency #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_stretcher #(parameter CYCLES = 5) // "wakeup" cycles
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( input clk, // clock
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input in, // input pulse
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input nreset, // async active low reset
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output out // stretched output pulse
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);
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reg [CYCLES-1:0] valid;
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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valid[CYCLES-1:0] <='b0;
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else if(in)
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valid[CYCLES-1:0] <={(CYCLES){1'b1}};
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else
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valid[CYCLES-1:0] <={valid[CYCLES-2:0],1'b0};
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assign out = valid[CYCLES-1];
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endmodule // oh_stretcher
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