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69f3df4140
-pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
30 lines
879 B
Verilog
30 lines
879 B
Verilog
module ereset (/*AUTOARG*/
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// Outputs
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reset, chip_resetb,
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// Inputs
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hard_reset, soft_reset
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);
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//inputs
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input hard_reset; // hardware reset from external block
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input soft_reset; // soft reset drive by register (level)
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//outputs
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output reset; //reset for elink
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output chip_resetb; //reset for epiphany
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//Reset for link logic
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assign reset = hard_reset | soft_reset;
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//May become more sophisticated later..
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//(for example, for epiphany reset, you might want to include some
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//some hard coded logic to avoid reset edge errata)
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//also, for multi chip boards, since the coordinates are sampled on
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//the rising edge of chip_resetb it may be beneficial to have one
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//reset per chip and to stagger the
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assign chip_resetb = ~(hard_reset | soft_reset);
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endmodule // ereset
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