Andreas Olofsson be42ea3b89 Register map change ...

-Changed register map
-Splitting into groups, more natural

2015-04-24 17:38:01 -04:00

..

ecfg_base.v

Adding IDs to keep access signals straight

2015-04-23 23:11:58 -04:00

ecfg_if.v

Register map change

2015-04-24 17:38:01 -04:00

ecfg_rx.v

Register map change

2015-04-24 17:38:01 -04:00

ecfg_tx.v

Register map change

2015-04-24 17:38:01 -04:00

ecfg.v

Message box working...

2015-04-19 21:55:07 -04:00

eclocks.v

Verilator based lint cleanup

2015-04-23 18:57:55 -04:00

elink_constants.v

Renaming constants file

2015-04-22 13:56:48 -04:00

elink_regmap.v

Register map change

2015-04-24 17:38:01 -04:00

elink.v

Adding IDs to keep access signals straight

2015-04-23 23:11:58 -04:00

emaxi.v

Bug fix, missing pipeline stage on read response

2015-04-21 17:14:30 -04:00

ememory.v

MILESTONE: Design once again passes test

2015-04-23 23:16:03 -04:00

ereset.v

Cleanup

2015-04-18 16:26:32 -04:00

erx_disty.v

Added tag and group for read response

2015-04-23 23:14:39 -04:00

erx_io.v

Verilator based lint cleanup

2015-04-23 18:57:55 -04:00

erx_mux.v

Readback cleanup

2015-04-24 17:27:35 -04:00

erx_protocol.v

Bug fix, adding reset signal

2015-04-23 23:13:05 -04:00

erx_remap.v

Adding RX/TX address remapping

2015-04-24 17:29:05 -04:00

erx.v

MILESTONE: Design once again passes test

2015-04-23 23:16:03 -04:00

esaxi.v

File cleanup

2015-04-23 18:10:07 -04:00

etx_arbiter.v

MILESTONE: Design once again passes test

2015-04-23 23:16:03 -04:00

etx_io.v

Clarified lclk names

2015-04-22 15:03:24 -04:00

etx_mux.v

Readback cleanup

2015-04-24 17:27:35 -04:00

etx_protocol.v

Verilator based lint cleanup

2015-04-23 18:57:55 -04:00

etx_remap.v

Adding RX/TX address remapping

2015-04-24 17:29:05 -04:00

etx.v

MILESTONE: Design once again passes test

2015-04-23 23:16:03 -04:00