mirror of
https://github.com/aolofsson/oh.git
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135 lines
3.7 KiB
Verilog
135 lines
3.7 KiB
Verilog
/*
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########################################################################
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ELINK CONFIGURATION INTERFACE
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########################################################################
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*/
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module ecfg_if (/*AUTOARG*/
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// Outputs
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rxrr_access, rxrr_packet, mi_clk, mi_en, mi_we, mi_addr, mi_din,
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// Inputs
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txwr_clk, txwr_access, txwr_packet, txrd_access, txrd_packet,
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rxrr_clk, mi_el_dout, mi_rx_dout, mi_tx_dout
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);
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parameter ID = 12'h800;
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parameter DW = 32;
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parameter AW = 32;
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parameter PW = 104;
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/******************************/
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/*Host Write Interface */
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/******************************/
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input txwr_clk; //write clock used as mi_clk
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input txwr_access;
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input [PW-1:0] txwr_packet;
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/******************************/
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/*Host Write Interface */
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/******************************/
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input txrd_access;
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input [PW-1:0] txrd_packet;
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/******************************/
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/*Host Readback Interface */
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/******************************/
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input rxrr_clk;
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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/******************************/
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/*Register Interface */
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/******************************/
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output mi_clk;
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output mi_en;
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output mi_we;
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output [19:0] mi_addr;
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output [31:0] mi_din;
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/******************************/
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/*Readback Data */
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/******************************/
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input [31:0] mi_el_dout;
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input [DW-1:0] mi_rx_dout;
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input [DW-1:0] mi_tx_dout;
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//wires
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wire [DW-1:0] txwr_data;
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wire [AW-1:0] txwr_dstaddr;
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wire [AW-1:0] txwr_srcaddr;
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wire [AW-1:0] txrd_dstaddr;
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wire [AW-1:0] txrd_srcaddr;
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wire mi_wr;
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wire mi_rd;
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//splicing packets
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packet2emesh p2e_wr(.access_out (),
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.write_out (),
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.datamode_out (),
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.ctrlmode_out (),
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.dstaddr_out (txwr_dstaddr[AW-1:0]),
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.data_out (txwr_data[DW-1:0]),
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.srcaddr_out (),
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.packet_in (txwr_packet[PW-1:0])
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);
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packet2emesh p2e_rd(.access_out (),
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.write_out (),
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.datamode_out (),
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.ctrlmode_out (),
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.dstaddr_out (txrd_dstaddr[AW-1:0]),
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.data_out (),
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.srcaddr_out (txrd_srcaddr[AW-1:0]),
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.packet_in (txrd_packet[PW-1:0])
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);
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//pass through clock
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//TODO: gate?
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assign mi_clk = txwr_clk;
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//Register file access (from slave)
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assign mi_wr = txwr_access & (txwr_dstaddr[31:20]==ID);
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assign mi_rd = txrd_access & (txrd_dstaddr[31:20]==ID);
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//Only 32 bit writes supported
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assign mi_we = mi_wr;
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assign mi_en = mi_wr | mi_rd;
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//Read/write address
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assign mi_addr[19:0] = mi_we ? txwr_dstaddr[19:0] :
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txrd_dstaddr[19:0];
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//Data
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assign mi_din[31:0] = txwr_data[31:0];
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//TODO: Do readback later....
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//
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endmodule // ecfg_if
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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