mirror of
https://github.com/aolofsson/oh.git
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112 lines
3.4 KiB
Verilog
112 lines
3.4 KiB
Verilog
/*###########################################################################
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# Function: High speed clock generator for elink
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#
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# cclk_p/n - Epiphany Output Clock (>600MHz)
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#
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# tx_lclk_div4 - Parallel data clock (125Mhz)
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#
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# tx_lclk - Serial DDR data clock (500MHz)
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#
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# tx_lclk90 - DDR "Clock" clock, to generate tx_lclk_p/n output
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# Same as lclk, shifted by 90 degrees
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#
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############################################################################
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*/
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module eclocks (/*AUTOARG*/
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// Outputs
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cclk_p, cclk_n, tx_lclk, tx_lclk90, tx_lclk_div4,
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// Inputs
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clkin, hard_reset, ecfg_clk_settings, clkbypass
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);
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// Parameters must be set as follows:
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// PFD input frequency = 1/CLKIN1_PERIOD / DIVCLK_DIVIDE (10-450MHz)
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// VCO frequency = PFD input frequency * CLKFBOUT_MULT (800-1600MHz)
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// Output frequency = VCO frequency / CLKOUTn_DIVIDE
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//Input clock, reset, config interface
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input clkin; // primary input clock
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input hard_reset; //
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input [15:0] ecfg_clk_settings; // clock settings
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input [2:0] clkbypass; // for bypassing PLL
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//Output Clocks
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output cclk_p, cclk_n; // high speed Epiphany clock (up to 1GHz)
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output tx_lclk; // elink tx serdes clock
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output tx_lclk90; // center aligned output clock for elink tx
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output tx_lclk_div4; // lclk/4 slow clock for tx parallel logic
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// Wires
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wire cclk_en;
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wire lclk_en;
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wire cclk;
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//Register decoding
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assign cclk_en=ecfg_clk_settings[0];
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assign lclk_en=ecfg_clk_settings[1];
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`ifdef TARGET_XILINX
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//instantiate MMCM
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`elsif TARGET_CLEAN
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clock_divider cclk_divider(
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// Outputs
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.clkout (cclk),
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.clkout90 (),
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// Inputs
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.clkin (clkin & cclk_en),
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.reset (hard_reset),
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.divcfg (ecfg_clk_settings[7:4])
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);
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clock_divider lclk_divider(
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// Outputs
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.clkout (tx_lclk),
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.clkout90 (tx_lclk90),
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// Inputs
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.clkin (clkin & lclk_en),
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.reset (hard_reset),
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.divcfg (ecfg_clk_settings[11:8])
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);
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clock_divider lclk_par_divider(
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// Outputs
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.clkout (tx_lclk_div4),
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.clkout90 (),
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// Inputs
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.clkin (clkin & lclk_en),
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.reset (hard_reset),
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.divcfg (ecfg_clk_settings[11:8] + 4'd2)
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);
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//Output buffer
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assign cclk_p = cclk & cclk_en ;
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assign cclk_n = ~cclk_p;
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`endif
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endmodule // eclocks
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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