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48 lines
1.7 KiB
Verilog
48 lines
1.7 KiB
Verilog
module ereset (/*AUTOARG*/
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// Outputs
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reset, chip_resetb,
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// Inputs
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hard_reset, soft_reset
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);
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//inputs
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input hard_reset; // hardware reset from external block
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input soft_reset; // soft reset drive by register (level)
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//outputs
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output reset; //reset for elink
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output chip_resetb; //reset for epiphany
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//Reset for link logic
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assign reset = hard_reset | soft_reset;
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//May become more sophisticated later..
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//(for example, for epiphany reset, you might want to include some
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//some hard coded logic to avoid reset edge errata)
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//also, for multi chip boards, since the coordinates are sampled on
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//the rising edge of chip_resetb it may be beneficial to have one
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//reset per chip and to stagger the
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assign chip_resetb = ~(hard_reset | soft_reset);
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endmodule // ereset
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Roman Trogan <roman@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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