mirror of
https://github.com/aolofsson/oh.git
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362 lines
14 KiB
Verilog
362 lines
14 KiB
Verilog
module etx(/*AUTOARG*/
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// Outputs
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mi_tx_emmu_dout, mi_tx_cfg_dout, txrd_wait, txwr_wait, txrr_wait,
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txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
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txo_data_n,
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// Inputs
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reset, tx_lclk, tx_lclk90, tx_lclk_div4, mi_clk, mi_en, mi_we,
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mi_addr, mi_din, txrd_clk, txrd_access, txrd_packet, txwr_clk,
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txwr_access, txwr_packet, txrr_clk, txrr_access, txrr_packet,
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txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter ID = 12'h0;
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//Clocks and reset
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input reset;
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input tx_lclk; // high speed serdes clock
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input tx_lclk90; // lclk for output
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input tx_lclk_div4; // slow speed parallel clock
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//Register Access Interface
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input mi_clk;
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input mi_en;
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input mi_we; // single we, must write 32 bit words
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input [19:0] mi_addr; // complete physical address (no shifting!)
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input [31:0] mi_din;
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output [DW-1:0] mi_tx_emmu_dout;
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output [DW-1:0] mi_tx_cfg_dout;
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//Slave Read Request (to TX)
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input txrd_clk;
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input txrd_access;
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input [PW-1:0] txrd_packet;
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output txrd_wait;
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//Slave Write (to TX)
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input txwr_clk;
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input txwr_access;
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input [PW-1:0] txwr_packet;
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output txwr_wait;
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//Master Read Response (to TX)
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input txrr_clk;
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input txrr_access;
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input [PW-1:0] txrr_packet;
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output txrr_wait;
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//Transmit signals for IO
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output txo_lclk_p, txo_lclk_n; //tx center aligned clock (>500MHz)
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output txo_frame_p, txo_frame_n; //tx frame signal
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output [7:0] txo_data_p, txo_data_n; //tx data (dual data rate)
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input txi_wr_wait_p,txi_wr_wait_n; //tx async write pushback
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input txi_rd_wait_p, txi_rd_wait_n; //tx async read pushback
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//debug declarations
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reg [15:0] ecfg_tx_debug;
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wire txwr_fifo_full;
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wire txrr_fifo_full;
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wire txrd_fifo_full;
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [8:0] ecfg_dataout; // From ecfg_tx of ecfg_tx.v
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wire [3:0] ecfg_tx_ctrlmode; // From ecfg_tx of ecfg_tx.v
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wire ecfg_tx_ctrlmode_bp; // From ecfg_tx of ecfg_tx.v
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wire ecfg_tx_enable; // From ecfg_tx of ecfg_tx.v
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wire ecfg_tx_gpio_enable; // From ecfg_tx of ecfg_tx.v
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wire ecfg_tx_mmu_enable; // From ecfg_tx of ecfg_tx.v
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wire ecfg_tx_tp_enable; // From ecfg_tx of ecfg_tx.v
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wire emmu_access; // From emmu of emmu.v
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wire [PW-1:0] emmu_packet; // From emmu of emmu.v
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wire etx_access; // From etx_arbiter of etx_arbiter.v
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wire etx_ack; // From etx_protocol of etx_protocol.v
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wire [PW-1:0] etx_packet; // From etx_arbiter of etx_arbiter.v
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wire etx_rd_wait; // From etx_protocol of etx_protocol.v
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wire etx_wr_wait; // From etx_protocol of etx_protocol.v
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wire [63:0] tx_data_par; // From etx_protocol of etx_protocol.v
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wire [7:0] tx_frame_par; // From etx_protocol of etx_protocol.v
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wire tx_rd_wait; // From etx_io of etx_io.v
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wire tx_wr_wait; // From etx_io of etx_io.v
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wire txrd_fifo_empty; // From txrd_fifo of fifo_async.v
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wire [PW-1:0] txrd_fifo_packet; // From txrd_fifo of fifo_async.v
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wire txrd_fifo_read; // From etx_arbiter of etx_arbiter.v
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wire txrr_fifo_empty; // From txrr_fifo of fifo_async.v
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wire [PW-1:0] txrr_fifo_packet; // From txrr_fifo of fifo_async.v
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wire txrr_fifo_read; // From etx_arbiter of etx_arbiter.v
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wire txwr_fifo_empty; // From txwr_fifo of fifo_async.v
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wire [PW-1:0] txwr_fifo_packet; // From txwr_fifo of fifo_async.v
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wire txwr_fifo_read; // From etx_arbiter of etx_arbiter.v
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// End of automatics
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/************************************************************/
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/* ETX CONFIGURATION */
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/************************************************************/
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defparam ecfg_tx.GROUP=`EGROUP_MMR;
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ecfg_tx ecfg_tx (
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.mi_dout (mi_tx_cfg_dout[31:0]),
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/*AUTOINST*/
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// Outputs
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.ecfg_tx_enable (ecfg_tx_enable),
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.ecfg_tx_mmu_enable (ecfg_tx_mmu_enable),
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.ecfg_tx_gpio_enable(ecfg_tx_gpio_enable),
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.ecfg_tx_tp_enable (ecfg_tx_tp_enable),
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.ecfg_tx_ctrlmode (ecfg_tx_ctrlmode[3:0]),
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.ecfg_tx_ctrlmode_bp(ecfg_tx_ctrlmode_bp),
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.ecfg_dataout (ecfg_dataout[8:0]),
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// Inputs
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.reset (reset),
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.mi_clk (mi_clk),
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.mi_en (mi_en),
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.mi_we (mi_we),
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.mi_addr (mi_addr[19:0]),
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.mi_din (mi_din[31:0]),
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.ecfg_tx_debug (ecfg_tx_debug[15:0]));
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/************************************************************/
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/*FIFOs */
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/************************************************************/
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//TODO: Minimize depth and width
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/*fifo_async AUTO_TEMPLATE (
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// Outputs
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.dout (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
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.empty (@"(substring vl-cell-name 0 4)"_fifo_empty),
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.full (@"(substring vl-cell-name 0 4)"_fifo_full),
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.prog_full (@"(substring vl-cell-name 0 4)"_fifo_prog_full),
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// Inputs
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.rd_clk (tx_lclk_div4),
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.wr_clk (@"(substring vl-cell-name 0 4)"_clk),
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.wr_en (@"(substring vl-cell-name 0 4)"_access),
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.rd_en (@"(substring vl-cell-name 0 4)"_fifo_read),
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.reset (reset),
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.din (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
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);
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*/
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//Write fifo (from slave)
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wire txwr_access_gated = txwr_access & ~(txwr_packet[39:28]==ID);
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fifo_async #(.DW(104), .AW(5)) txwr_fifo(.wr_en (txwr_access_gated),
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.prog_full (txwr_wait),
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.full (txwr_fifo_full),
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/*AUTOINST*/
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// Outputs
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.dout (txwr_fifo_packet[PW-1:0]), // Templated
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.empty (txwr_fifo_empty), // Templated
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// Inputs
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.reset (reset), // Templated
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.wr_clk (txwr_clk), // Templated
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.rd_clk (tx_lclk_div4), // Templated
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.din (txwr_packet[PW-1:0]), // Templated
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.rd_en (txwr_fifo_read)); // Templated
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//Read request fifo (from slave)
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wire txrd_access_gated = txrd_access & ~(txrd_packet[39:28]==ID);
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fifo_async #(.DW(104), .AW(5)) txrd_fifo(.wr_en (txrd_access_gated),
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.prog_full (txrd_wait),
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.full (txrd_fifo_full),
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/*AUTOINST*/
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// Outputs
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.dout (txrd_fifo_packet[PW-1:0]), // Templated
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.empty (txrd_fifo_empty), // Templated
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// Inputs
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.reset (reset), // Templated
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.wr_clk (txrd_clk), // Templated
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.rd_clk (tx_lclk_div4), // Templated
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.din (txrd_packet[PW-1:0]), // Templated
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.rd_en (txrd_fifo_read)); // Templated
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//Read response fifo (from master)
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fifo_async #(.DW(104), .AW(5)) txrr_fifo(
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.prog_full (txrr_wait),
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.full (txrr_fifo_full),
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/*AUTOINST*/
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// Outputs
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.dout (txrr_fifo_packet[PW-1:0]), // Templated
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.empty (txrr_fifo_empty), // Templated
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// Inputs
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.reset (reset), // Templated
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.wr_clk (txrr_clk), // Templated
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.rd_clk (tx_lclk_div4), // Templated
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.wr_en (txrr_access), // Templated
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.din (txrr_packet[PW-1:0]), // Templated
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.rd_en (txrr_fifo_read)); // Templated
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/************************************************************/
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/*ELINK TRANSMIT ARBITER */
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/************************************************************/
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defparam etx_arbiter.ID=ID;
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etx_arbiter etx_arbiter (
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/*AUTOINST*/
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// Outputs
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.txwr_fifo_read (txwr_fifo_read),
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.txrd_fifo_read (txrd_fifo_read),
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.txrr_fifo_read (txrr_fifo_read),
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.etx_access (etx_access),
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.etx_packet (etx_packet[PW-1:0]),
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// Inputs
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.tx_lclk_div4 (tx_lclk_div4),
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.reset (reset),
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.ecfg_tx_ctrlmode_bp(ecfg_tx_ctrlmode_bp),
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.ecfg_tx_ctrlmode (ecfg_tx_ctrlmode[3:0]),
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.txwr_fifo_empty (txwr_fifo_empty),
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.txwr_fifo_packet (txwr_fifo_packet[PW-1:0]),
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.txrd_fifo_empty (txrd_fifo_empty),
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.txrd_fifo_packet (txrd_fifo_packet[PW-1:0]),
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.txrr_fifo_empty (txrr_fifo_empty),
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.txrr_fifo_packet (txrr_fifo_packet[PW-1:0]),
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.etx_rd_wait (etx_rd_wait),
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.etx_wr_wait (etx_wr_wait),
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.etx_ack (etx_ack));
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/************************************************************/
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/* EMMU */
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/************************************************************/
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/*emmu AUTO_TEMPLATE (
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.emmu_packet_out (emmu_packet[PW-1:0]),
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.emesh_\(.*\)_in (etx_\1[]),
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.mmu_en (ecfg_tx_mmu_enable),
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.clk (tx_lclk_div4),
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.emmu_access_out (emmu_access),
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.emmu_packet_out (emmu_packet[PW-1:0]),
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.mi_dout (mi_tx_emmu_dout[DW-1:0]),
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);
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*/
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defparam emmu.GROUP=`EGROUP_TXMMU;
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emmu emmu (.emmu_packet_hi_out (),
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_tx_emmu_dout[DW-1:0]), // Templated
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.emmu_access_out (emmu_access), // Templated
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.emmu_packet_out (emmu_packet[PW-1:0]), // Templated
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// Inputs
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.clk (tx_lclk_div4), // Templated
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.reset (reset),
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.mmu_en (ecfg_tx_mmu_enable), // Templated
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.mi_clk (mi_clk),
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.mi_en (mi_en),
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.mi_we (mi_we),
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.mi_addr (mi_addr[19:0]),
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.mi_din (mi_din[DW-1:0]),
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.emesh_access_in (etx_access), // Templated
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.emesh_packet_in (etx_packet[PW-1:0])); // Templated
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/************************************************************/
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/*ELINK PROTOCOL LOGIC */
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/************************************************************/
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/*etx_protocol AUTO_TEMPLATE (
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.etx_ack (etx_ack),
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.etx_rd_wait (etx_rd_wait),
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.etx_wr_wait (etx_wr_wait),
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.etx_\(.*\) (emmu_\1[]),
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);
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*/
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etx_protocol etx_protocol (/*AUTOINST*/
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// Outputs
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.etx_rd_wait (etx_rd_wait), // Templated
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.etx_wr_wait (etx_wr_wait), // Templated
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.etx_ack (etx_ack), // Templated
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.tx_frame_par (tx_frame_par[7:0]),
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.tx_data_par (tx_data_par[63:0]),
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// Inputs
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.etx_access (emmu_access), // Templated
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.etx_packet (emmu_packet[PW-1:0]), // Templated
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.ecfg_tx_tp_enable(ecfg_tx_tp_enable),
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.reset (reset),
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.tx_lclk_div4 (tx_lclk_div4),
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.tx_rd_wait (tx_rd_wait),
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.tx_wr_wait (tx_wr_wait));
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/***********************************************************/
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/*ELINK TRANSMIT I/O LOGIC */
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/***********************************************************/
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etx_io etx_io (
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/*AUTOINST*/
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// Outputs
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.txo_lclk_p (txo_lclk_p),
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.txo_lclk_n (txo_lclk_n),
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.txo_frame_p (txo_frame_p),
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.txo_frame_n (txo_frame_n),
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.txo_data_p (txo_data_p[7:0]),
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.txo_data_n (txo_data_n[7:0]),
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.tx_wr_wait (tx_wr_wait),
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.tx_rd_wait (tx_rd_wait),
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// Inputs
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.reset (reset),
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.txi_wr_wait_p (txi_wr_wait_p),
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.txi_wr_wait_n (txi_wr_wait_n),
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.txi_rd_wait_p (txi_rd_wait_p),
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.txi_rd_wait_n (txi_rd_wait_n),
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.tx_lclk_div4 (tx_lclk_div4),
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.tx_lclk (tx_lclk),
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.tx_lclk90 (tx_lclk90),
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.tx_frame_par (tx_frame_par[7:0]),
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.tx_data_par (tx_data_par[63:0]),
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.ecfg_tx_enable (ecfg_tx_enable),
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.ecfg_tx_gpio_enable (ecfg_tx_gpio_enable),
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.ecfg_dataout (ecfg_dataout[8:0]));
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/************************************************************/
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/*Debug signals (async sampling) */
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/************************************************************/
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always @ (posedge mi_clk)
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begin
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ecfg_tx_debug[15:0] <= {2'b0, //15:14
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etx_rd_wait, //13
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etx_wr_wait, //12
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txrr_fifo_read, //11
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txrr_wait, //10
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txrr_access, //9
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txrd_fifo_read, //8
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txrd_wait, //7
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txrd_access, //6
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txwr_fifo_read, //5
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txwr_wait, //4
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txwr_access, //3
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txrr_fifo_full, //2
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txrd_fifo_full, //1
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txwr_fifo_full //0
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};
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end
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endmodule // elink
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// Local Variables:
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// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl")
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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