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ea7683693c
The MMU is a monster and may be too much Adding simple remapping modules Covers todays feature and then some 1.) Static remapping 2.) Addresss compression
58 lines
1.5 KiB
Verilog
58 lines
1.5 KiB
Verilog
module etx_remap (/*AUTOARG*/
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// Outputs
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emesh_access_out, emesh_packet_out,
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// Inputs
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clk, reset, emesh_access_in, emesh_packet_in, remap_en,
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remap_bypass, emesh_wait_in
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter ID = 12'h808;
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//Clock/reset
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input clk;
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input reset;
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//Input from arbiter
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input emesh_access_in;
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input [PW-1:0] emesh_packet_in;
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input remap_en; //enable tx remap (static)
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input remap_bypass; //dynamic control (read request)
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//Output to TX IO
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output emesh_access_out;
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output [PW-1:0] emesh_packet_out;
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input emesh_wait_in;
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wire [31:0] addr_in;
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wire [31:0] addr_remap;
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wire [31:0] addr_out;
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reg emesh_access_out;
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reg [PW-1:0] emesh_packet_out;
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assign addr_in[31:0] = emesh_packet_in[39:8];
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assign addr_remap[31:0] = {addr_in[28:17],
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{(4){addr_in[16]}},
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addr_in[15:0]
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};
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assign addr_out[31:0] = (remap_en & ~remap_bypass) ? addr_remap[31:0] :
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addr_in[31:0];
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always @ (posedge clk)
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if(~emesh_wait_in)//pipeline stall
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begin
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emesh_access_out <= emesh_access_in;
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emesh_packet_out[PW-1:0] <= {emesh_packet_in[PW-1:40],
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addr_out[31:0],
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emesh_packet_in[7:0]
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};
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end
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endmodule // etx_mux
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