Andreas Olofsson fa42bc6e2e Reset simulation issue ...

- Feels like I have seen this before, but still makes me nervous. The async negedge of reset was never being triggered in simulation by iverilog, probably because the simulation initialized it to 0, so there was no negedge. In logic, this is an async level signal....

2016-01-11 20:47:06 -05:00

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build.sh

Adding missing files

2015-11-03 14:16:50 -05:00

dut.v

Making AW main parameter

2016-01-11 15:05:21 -05:00

dv_ctrl.v

Reset simulation issue

2016-01-11 20:47:06 -05:00

dv_driver.v

Error message in one hot mux

2016-01-11 17:35:15 -05:00

dv_random.v

Moving to MIT license

2015-11-06 11:25:05 -05:00

dv_top.v

Making AW main parameter

2016-01-11 15:05:21 -05:00

libs.cmd

Moving axi cells to own folder

2015-12-04 03:38:26 -05:00

run.sh

Adding missing files

2015-11-03 14:16:50 -05:00

stimulus.v

Changing emesh stimulus suffix ti "*.emf"

2016-01-10 11:57:38 -05:00

timescale.v

Adding missing files

2015-11-03 14:16:50 -05:00