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233 lines
9.2 KiB
Verilog
233 lines
9.2 KiB
Verilog
/*###########################################################################
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# Function: High speed clock generator elink module
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#
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# cclk_p/n - Epiphany Core Clock, Differential, must be connected
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# directly to IO pins.
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#
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# tx_lclk_par - Parallel data clock, at bit rate / 8 for etx
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#
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# tx_lclk - Serial DDR data clock, at bit rate / 2 for etx
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#
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# tx_lclk_out - DDR "Clock" clock, to generate tx_lclk_p/n output
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# At bit rate / 2, 90deg shifted from tx_lclk
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#
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# Notes: Uses Xilinx macros throughout
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#
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############################################################################
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*/
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`timescale 1ns/1ps
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module eclock (/*AUTOARG*/
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// Outputs
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cclk_p, cclk_n, tx_lclk, tx_lclk_out, tx_lclk_par,
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// Inputs
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clkin, reset, ecfg_cclk_en, ecfg_cclk_div, ecfg_cclk_pllcfg,
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ecfg_cclk_bypass, ecfg_tx_clkbypass
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);
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// Parameters must be set as follows:
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// PFD input frequency = 1/CLKIN1_PERIOD / DIVCLK_DIVIDE (10-450MHz)
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// VCO frequency = PFD input frequency * CLKFBOUT_MULT (800-1600MHz)
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// Output frequency = VCO frequency / CLKOUTn_DIVIDE
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parameter CLKIN_PERIOD = 10.000; // ns -> 100MHz
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parameter CLKIN_DIVIDE = 1;
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parameter VCO_MULT = 12; // VCO = 1200MHz
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parameter CCLK_DIVIDE = 2; // CCLK = 600MHz
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parameter LCLK_DIVIDE = 4; // LCLK = 300MHz (600MB/s eLink)
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parameter FEATURE_CCLK_DIV = 1'b1;
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parameter IOSTD_ELINK = "LVDS_25";
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//Input clock & reset
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input clkin;
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input reset;
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//From configuration register
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input ecfg_cclk_en; //cclk enable
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input [3:0] ecfg_cclk_div; //cclk divider setting
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input [3:0] ecfg_cclk_pllcfg; //pll configuration TODO: ??
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input ecfg_cclk_bypass; //ccclk==clkin
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input ecfg_tx_clkbypass; //tx_lclk==clkin (need manual divider for lclk_out)
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//Epiphany clock
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output cclk_p, cclk_n; //high speed clock directly to pin
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//Transmit clocks
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output tx_lclk; //for serialized in transmit serdes
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output tx_lclk_out; //for lclk output
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output tx_lclk_par; //slow clock for tx parallel logic
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// Wires
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wire clkfb;
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wire pll_cclk; //full speed cclk
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wire pll_lclk; //full speed lclk etx
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wire pll_lclk_out; //full speed lclk for pin for etx
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wire pll_lclk_par; //low speed lclk for etx
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wire pll_cclk_div; //low speed cclk
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wire pll_cclk_standby; //standby clock
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wire cclk;
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wire cclk_base;
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wire cclk_div;
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// PLL Primitive
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PLLE2_BASE
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#(
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.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
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.CLKFBOUT_MULT(VCO_MULT), // Multiply value for all CLKOUT, (2-64)
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
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.CLKIN1_PERIOD(CLKIN_PERIOD),// Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
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// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
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.CLKOUT0_DIVIDE(CCLK_DIVIDE), //full speed
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.CLKOUT1_DIVIDE(LCLK_DIVIDE), //full speed
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.CLKOUT2_DIVIDE(LCLK_DIVIDE), //full speed
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.CLKOUT3_DIVIDE(LCLK_DIVIDE * 4), //low speed
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.CLKOUT4_DIVIDE(CCLK_DIVIDE * 4), //low speed
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.CLKOUT5_DIVIDE(128), //veeery low speed
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// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(90.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.DIVCLK_DIVIDE(CLKIN_DIVIDE),// Master division value, (1-56)
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.REF_JITTER1(0.01), // Reference input jitter (0.000-0.999).
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.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
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) eclk_pll
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(
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// Clock Outputs: 1-bit (each) output: User configurable clock outputs
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.CLKOUT0(pll_cclk), //full speed cclk
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.CLKOUT1(pll_lclk), //full speed lclk etx
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.CLKOUT2(pll_lclk_out), //full speed lclk for pin for etx
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.CLKOUT3(pll_lclk_par), //low speed lclk for etx
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.CLKOUT4(pll_cclk_div), //low speed cclk
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.CLKOUT5(pll_cclk_standby), //standby clock
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.CLKFBOUT(clkfb), //feedback clock output
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.LOCKED(), //lock signal
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.CLKIN1(clkin), //main input clock
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.PWRDWN(1'b0), //pll power down
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.RST(1'b0), //reset
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.CLKFBIN(clkfb) //feedback clock input
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);
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// Output buffering
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BUFG cclk_buf (.O (cclk_base), .I (pll_cclk));
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BUFG cclk_div_buf (.O (cclk_div), .I (pll_cclk_div));
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BUFG lclk_buf (.O (tx_lclk), .I (pll_lclk));
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BUFG lclk_out_buf (.O (tx_lclk_out), .I (pll_lclk_out));
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BUFG lclk_par_buf (.O (tx_lclk_par), .I (pll_lclk_par));
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generate
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if( FEATURE_CCLK_DIV ) begin : gen_cclk_div
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// Create adjustable (but fast) CCLK
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wire rxi_cclk_out;
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reg [8:1] cclk_pattern;
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reg [3:0] clk_div_sync;
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reg enb_sync;
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always @ (posedge cclk_div) begin // Might need x-clock TIG here
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clk_div_sync <= ecfg_cclk_div;
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enb_sync <= ecfg_cclk_en;
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if(enb_sync)
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case(clk_div_sync)
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4'h0: cclk_pattern <= 8'd0; // Clock OFF
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4'h7: cclk_pattern <= 8'b10101010; // Divide by 1
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4'h6: cclk_pattern <= 8'b11001100; // Divide by 2
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4'h5: cclk_pattern <= 8'b11110000; // Divide by 4
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default: cclk_pattern <= {8{~cclk_pattern[1]}}; // /8
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endcase
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else
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cclk_pattern <= 8'b00000000;
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end // always @ (posedge cclk_div)
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//CCLK CLOCK DIVIDER
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OSERDESE2
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#(
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.DATA_RATE_OQ("DDR"), // DDR, SDR
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.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
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.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
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.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
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.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
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.SERDES_MODE("MASTER"), // MASTER, SLAVE
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.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
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.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
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.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
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.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
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.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
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) OSERDESE2_inst
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(
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.OFB(), // Feedback path for data
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.OQ(cclk), // Data path output
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.SHIFTOUT1(),
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.SHIFTOUT2(),
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.TBYTEOUT(), // Byte group tristate
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.TFB(), // 1-bit output: 3-state control
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.TQ(), // 3-state control
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.CLK(cclk_base), // High speed clock
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.CLKDIV(cclk_div), // Divided clock
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.D1(cclk_pattern[1]), // Parallel data inputs
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.D2(cclk_pattern[2]),
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.D3(cclk_pattern[3]),
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.D4(cclk_pattern[4]),
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.D5(cclk_pattern[5]),
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.D6(cclk_pattern[6]),
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.D7(cclk_pattern[7]),
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.D8(cclk_pattern[8]),
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.OCE(1'b1), // Output data clock enable TODO: gating?
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.RST(reset), // Reset
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.SHIFTIN1(1'b0), // Data input expansion (1-bit each)
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.SHIFTIN2(1'b0),
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.T1(1'b0), // Parallel 3-state inputs
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.T2(1'b0),
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.T3(1'b0),
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.T4(1'b0),
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.TBYTEIN(1'b0), // Byte group tristate
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.TCE(1'b0) // 3-state clock enable
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);
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end else
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begin : gen_fixed_cclk // Non-dividable CCLK
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reg enb_sync;
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always @ (posedge cclk_div)
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enb_sync <= ecfg_cclk_en;
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// The following does not result in timing failures,
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// but doesn't seem glitch-safe
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assign cclk = cclk_base & enb_sync;
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end
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endgenerate
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//Clock output
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OBUFDS #(.IOSTANDARD (IOSTD_ELINK)) obufds_cclk_inst (.O (cclk_p), .OB (cclk_n), .I (cclk));
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endmodule // eclock
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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