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https://github.com/aolofsson/oh.git
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befc18f368
-Fixes issue with back to back transactions! -Read/writes work!! -Needs more verification/analysis...
219 lines
6.3 KiB
Verilog
219 lines
6.3 KiB
Verilog
module etx_io (/*AUTOARG*/
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// Outputs
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txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
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txo_data_n, tx_io_wait, tx_wr_wait, tx_rd_wait,
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// Inputs
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ioreset, tx_lclk, tx_lclk90, tx_lclk_div4, txi_wr_wait_p,
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txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n, tx_packet, tx_access,
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tx_burst
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);
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parameter IOSTD_ELINK = "LVDS_25";
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parameter PW = 104;
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//###########
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//# reset, clocks
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//##########
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input ioreset; //reset for io
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input tx_lclk; // fast clock for io
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input tx_lclk90; // fast 90deg shifted lclk
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input tx_lclk_div4; // slow clock for rest of logic
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//###########
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//# eLink pins
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//###########
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output txo_lclk_p, txo_lclk_n; // tx clock output
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output txo_frame_p, txo_frame_n; // tx frame signal
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output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
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input txi_wr_wait_p,txi_wr_wait_n; // tx write pushback
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input txi_rd_wait_p, txi_rd_wait_n; // tx read pushback
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//#############
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//# Fabric interface
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//#############
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input [PW-1:0] tx_packet;
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input tx_access;
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input tx_burst;
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output tx_io_wait;
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output tx_wr_wait;
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output tx_rd_wait;
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//############
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//# REGS
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//############
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reg [7:0] tx_pointer;
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reg [15:0] tx_data16;
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reg [7:0] tx_data;
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reg tx_access_reg;
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reg tx_frame;
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reg tx_io_wait_reg;
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//############
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//# WIRES
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//############
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wire new_tran;
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wire access;
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wire write;
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wire [1:0] datamode;
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wire [3:0] ctrlmode;
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wire [31:0] dstaddr;
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wire [31:0] data;
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wire [31:0] srcaddr;
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//#############################
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//# Disassemble packet (for clarity)
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//#############################
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packet2emesh p2e (
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// Outputs
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.access_out (access),
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.write_out (write),
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.datamode_out (datamode[1:0]),
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.ctrlmode_out (ctrlmode[3:0]),
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.dstaddr_out (dstaddr[31:0]),
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.data_out (data[31:0]),
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.srcaddr_out (srcaddr[31:0]),
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// Inputs
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.packet_in (tx_packet[PW-1:0]));
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//#############################
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//# Transaction state machine
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//#############################
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always @ (posedge tx_lclk)
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if (~tx_access)
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tx_pointer[7:0] <= 8'b00000001; //new transaction
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else if (tx_pointer[6] & tx_burst)
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tx_pointer[7:0] <= 8'b00001000; //burst
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else
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tx_pointer[7:0] <= {tx_pointer[6:0],tx_pointer[7]};
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//#############################
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//# Frame Signal
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//#############################
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//TODO: cleanup
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assign tx_io_wait = tx_access & ~tx_burst & ~tx_io_wait_reg;
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always @ (posedge tx_lclk_div4 or posedge ioreset)
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if(ioreset)
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tx_io_wait_reg <= 1'b0;
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else
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tx_io_wait_reg <= tx_io_wait;
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//#############################
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//# Frame Signal
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//#############################
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always @ (posedge tx_lclk or posedge ioreset)
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if(ioreset)
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tx_frame <= 1'b0;
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else if(tx_pointer[0] & tx_access)
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tx_frame <= 1'b1;
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else if(tx_pointer[7] & ~tx_burst)
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tx_frame <= 1'b0;
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//#############################
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//# SELECTING DATA PER CYCLE
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//#############################
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//optimize later...
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always @ (negedge tx_lclk)
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case(tx_pointer[6:0])
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//Cycle0
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7'b0000001: tx_data16[15:0] <= {ctrlmode[3:0],dstaddr[31:28],~write,7'b0};
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//Cycle1
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7'b0000010: tx_data16[15:0] <= {dstaddr[19:12],dstaddr[27:20]};
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//Cycle2
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7'b0000100: tx_data16[15:0] <= {dstaddr[3:0],datamode[1:0],write,access,
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dstaddr[11:4]};
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//Cycle3
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7'b0001000: tx_data16[15:0] <= {data[23:16],data[31:24]};
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//Cycle4
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7'b0010000: tx_data16[15:0] <= {data[7:0],data[15:8]};
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//Cycle5
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7'b0100000: tx_data16[15:0] <= {srcaddr[23:16],srcaddr[31:24]};
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//Cycle6
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7'b1000000: tx_data16[15:0] <= {srcaddr[7:0],srcaddr[15:8]};
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default tx_data16[15:0] <= 16'b0;
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endcase // case (tx_pointer[7:0])
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//#############################
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//# DATA (DDR)
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//#############################
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always @ (negedge tx_lclk)
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tx_data[7:0] <= tx_data16[15:8];
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always @ (posedge tx_lclk)
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tx_data[7:0] <= tx_data16[7:0];
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//##############################
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//# OUTPUT BUFFERS
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//##############################
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OBUFDS obufds_data[7:0] (
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.O (txo_data_p[7:0]),
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.OB (txo_data_n[7:0]),
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.I (tx_data)
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);
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OBUFDS obufds_frame ( .O (txo_frame_p),
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.OB (txo_frame_n),
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.I (tx_frame)
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);
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OBUFDS obufds_lclk ( .O (txo_lclk_p),
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.OB (txo_lclk_n),
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.I (tx_lclk90)
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);
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//################################
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//# Wait Input Buffers
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//################################
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IBUFDS
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#(.DIFF_TERM ("TRUE"), // Differential termination
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.IOSTANDARD (IOSTD_ELINK))
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ibufds_wrwait
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(.I (txi_wr_wait_p),
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.IB (txi_wr_wait_n),
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.O (tx_wr_wait));
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//TODO: Come up with cleaner defines for this
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//Parallella and other platforms...
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`ifdef TODO
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IBUFDS
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#(.DIFF_TERM ("TRUE"), // Differential termination
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.IOSTANDARD (IOSTD_ELINK))
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ibufds_rdwait
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(.I (txi_rd_wait_p),
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.IB (txi_rd_wait_n),
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.O (tx_rd_wait));
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`else
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//On Parallella this signal comes in single-ended
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assign tx_rd_wait = txi_rd_wait_p;
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`endif
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endmodule // etx_io
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl")
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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