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bf1671b1e9
-Icarus for now, verilator comes next -Using our "standard" emesh interface ..here we go...
113 lines
3.0 KiB
Verilog
113 lines
3.0 KiB
Verilog
module dv_elink_tb();
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//REGS
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reg clk;
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reg reset;
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reg go;
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reg ext_access;
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reg ext_write;
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reg [1:0] ext_datamode;
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reg [3:0] ext_ctrlmode;
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reg [31:0] ext_dstaddr;
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reg [31:0] ext_data;
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reg [31:0] ext_srcaddr;
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reg ext_wr_wait;
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reg ext_rd_wait;
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//Forever clock
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always
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#10 clk = ~clk;
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//Reset
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initial
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begin
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#0
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reset = 1'b1; // reset is active
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go = 1'b0;
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clk = 1'b0;
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#100
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reset = 1'b0; // at time 100 release reset
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#500
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go =1'b1;
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#10000
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$finish;
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end
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always @ (posedge clk)
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if(reset)
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begin
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ext_access <=1'b0;
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ext_write <=1'b0;
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ext_datamode[1:0] <=2'b0;
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ext_ctrlmode[3:0] <=4'b0;
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ext_data[31:0] <=32'b0;
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ext_dstaddr[31:0] <=32'b0;
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ext_srcaddr[31:0] <=32'b0;
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ext_rd_wait <=1'b0;
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ext_wr_wait <=1'b0;
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end
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else if(go)
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begin
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ext_access <=1'b1;
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ext_write <=1'b1;
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ext_datamode[1:0] <=2'b0;
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ext_ctrlmode[3:0] <=4'b0;
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ext_data[31:0] <=ext_data[31:0]+1'b1;
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ext_dstaddr[31:0] <=ext_dstaddr[31:0]+1'b1;
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ext_srcaddr[31:0] <=ext_srcaddr[31:0]+1'b1;
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end
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//Waveform dump
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initial
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begin
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$dumpfile("test.vcd");
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$dumpvars(0, dv_elink_tb);
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end
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire dut_access; // From dv_elink of dv_elink.v
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wire [3:0] dut_ctrlmode; // From dv_elink of dv_elink.v
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wire [31:0] dut_data; // From dv_elink of dv_elink.v
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wire [1:0] dut_datamode; // From dv_elink of dv_elink.v
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wire [31:0] dut_dstaddr; // From dv_elink of dv_elink.v
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wire dut_failed; // From dv_elink of dv_elink.v
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wire dut_passed; // From dv_elink of dv_elink.v
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wire dut_rd_wait; // From dv_elink of dv_elink.v
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wire [31:0] dut_srcaddr; // From dv_elink of dv_elink.v
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wire dut_wr_wait; // From dv_elink of dv_elink.v
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wire dut_write; // From dv_elink of dv_elink.v
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// End of automatics
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//dut
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dv_elink dv_elink(/*AUTOINST*/
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// Outputs
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.dut_passed (dut_passed),
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.dut_failed (dut_failed),
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.dut_wr_wait (dut_wr_wait),
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.dut_rd_wait (dut_rd_wait),
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.dut_access (dut_access),
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.dut_write (dut_write),
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.dut_datamode (dut_datamode[1:0]),
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.dut_ctrlmode (dut_ctrlmode[3:0]),
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.dut_dstaddr (dut_dstaddr[31:0]),
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.dut_srcaddr (dut_srcaddr[31:0]),
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.dut_data (dut_data[31:0]),
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// Inputs
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.clk (clk),
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.reset (reset),
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.ext_access (ext_access),
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.ext_write (ext_write),
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.ext_datamode (ext_datamode[1:0]),
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.ext_ctrlmode (ext_ctrlmode[3:0]),
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.ext_dstaddr (ext_dstaddr[31:0]),
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.ext_data (ext_data[31:0]),
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.ext_srcaddr (ext_srcaddr[31:0]),
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.ext_wr_wait (ext_wr_wait),
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.ext_rd_wait (ext_rd_wait));
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endmodule // dv_elink_tb
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