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998f3021cc
-Ultrascale changes broke the zynq design -Adding CFG_PLATFORM variable to control compilation target
33 lines
715 B
Bash
Executable File
33 lines
715 B
Bash
Executable File
#!/bin/bash
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############################################################################
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# Icarus Verilog build script for OH!
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#
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# Requires $OH_HOME variable to be set
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#
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# Example: ./scripts/build.sh elink/hdl/dut_elink.v
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#
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############################################################################
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DUT=$1
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##############################
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#Create directory of all links
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##############################
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$OH_HOME/scripts/link.sh
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##############################
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#Build
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###############################
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iverilog -g2005\
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-DTARGET_SIM=1\
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-DCFG_ASIC=0\
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-DCFG_PLATFORM=\"ZYNQ\"\
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$DUT\
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$OH_HOME/symlinks/dv/dv_top.v\
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-y .\
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-y $OH_HOME/symlinks/hdl\
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-y $OH_HOME/symlinks/dv\
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-I $OH_HOME/symlinks/hdl\
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-o dut.bin\
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