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31 lines
973 B
Verilog
31 lines
973 B
Verilog
//#############################################################################
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//# Function: Binary to gray encoder #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_bin2gray #(parameter DW = 32 // width of data inputs
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)
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(
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input [DW-1:0] in, //binary encoded input
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output [DW-1:0] out //gray encoded output
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);
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reg [DW-1:0] gray;
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wire [DW-1:0] bin;
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integer i;
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assign bin[DW-1:0] = in[DW-1:0];
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assign out[DW-1:0] = gray[DW-1:0];
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always @*
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begin
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gray[DW-1] = bin[DW-1];
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for (i=0; i<(DW-1); i=i+1)
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gray[i] = bin[i] ^ bin[i+1];
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end
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endmodule // oh_bin2gray
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