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6d1735d3b9
-Better to fix to avoid issues across different synthesis platform (even if standard would allow if for verilog2005)
28 lines
879 B
Verilog
28 lines
879 B
Verilog
//#############################################################################
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//# Function: Binary to one hot encoder #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_bin2onehot #(parameter N = 2, // output vector width
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parameter NB = $clog2(N) // binary encoded input
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)
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(
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input [NB-1:0] in, // unsigned binary input
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output [N-1:0] out // one hot output vector
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);
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genvar i;
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for(i=0;i<N;i=i+1) begin: gen_onehot
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assign out[i] = (in[NB-1:0] == i);
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end
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endmodule // oh_bin2onehot
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