mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
14 lines
222 B
Verilog
14 lines
222 B
Verilog
odule OBUFTDS_DCIEN (O, OB, DCITERMDISABLE, I, T);
|
|
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SLEW = "SLOW";
|
|
|
|
output O;
|
|
output OB;
|
|
|
|
input DCITERMDISABLE;
|
|
input I;
|
|
input T;
|
|
|
|
endmodule
|