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38 lines
1.2 KiB
Verilog
38 lines
1.2 KiB
Verilog
//#############################################################################
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//# Function: Clock synchronizer #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_dsync #(parameter PS = 2, // number of sync stages
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parameter DELAY = 0 // random delay
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)
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(
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input clk, // clock
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input nreset, // clock
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input din, // input data
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output dout // synchronized data
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);
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`ifdef CFG_ASIC
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asic_dsync asic_dsync (.clk(clk),
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.nreset(nreset),
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.din(din),
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.dout(dout));
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`else
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reg [PS:0] sync_pipe;
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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sync_pipe[PS:0] <= 1'b0;
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else
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sync_pipe[PS:0] <= {sync_pipe[PS-1:0],din};
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// drive randomize delay from testbench
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assign dout = (DELAY & sync_pipe[PS]) | //extra cycle
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(~DELAY & sync_pipe[PS-1]); //default
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`endif // !`ifdef CFG_ASIC
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endmodule // oh_dsync
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