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30 lines
1.1 KiB
Verilog
30 lines
1.1 KiB
Verilog
//#############################################################################
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//# Purpose: Serial to Parallel Converter #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_ser2par #(parameter PW = 64, // parallel packet width
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parameter SW = 1, // serial packet width
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parameter CW = $clog2(PW/SW) // serialization factor (for counter)
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)
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(
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input clk, // sampling clock
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input [SW-1:0] din, // serial data
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output reg [PW-1:0] dout, // parallel data
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input lsbfirst, // lsb first order
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input shift // shift the shifter
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);
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reg [CW-1:0] count;
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wire [PW-1:0] shiftdata;
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always @ (posedge clk)
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if(shift & lsbfirst)
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dout[PW-1:0] <= {din[SW-1:0],dout[PW-1:SW]};
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else if(shift)
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dout[PW-1:0] <= {dout[PW-SW-1:0],din[SW-1:0]};
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endmodule // oh_ser2par
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