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OH! Open hardware for Chips and FPGAs

CONTENT

FOLDER	STATUS	DESCRIPTION
accelerator	FPGA	Accelerator tutorial
axi	FPGA	AXI master and slave interfaces
chip	SI	Chip design reference flow
common	SI	Library of basic components
elink	SI	Point to point LVDS link
emailbox	FPGA	Mailbox with interrupt output
emesh	SI	Emesh interface utility circuits
emmu	FPGA	Memory transaction translation unit
etrace	HH	Logic Analyzer
gpio	HH	General Purpose IO
irqc	SI	Epiphany nested interrupt controller
parallella	FPGA	Parallella FPGA logic
risc-v	HH	RISC-V implementation
spi	HH	SPI master/slave
verilog	HH	Verilog referenca material
xilibs	FPGA	Xilinx simulation models

NOTES:

• "SI"= Silicon validated
• "FPGA" = FPGA validated
• "HH" = Hard hat area (work in progress)

LICENSE

The OH! repository source code is licensed under the MIT license unless otherwise specified. See LICENSE for MIT copyright terms. Design specific licenses can be found in the folder root (eg: aes/LICENSE)

CONTRIBUTING

Instructions for contributing can be found HERE.

REFERENCES MANUALS

• Verilog Reference
• Verilog Coding Methodology
• Glossary
• Chip constants

RECOMMENDED TOOLS

• Verilator Simulator
• Emacs Verilog Mode
• Icarus Simulator
• GTKWave
• Wavedrom
• FuseSoC

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