Andreas Olofsson c4c1edc10f Adding reset to critical signals in pipe

2015-04-23 20:06:11 -04:00

..

ecfg_base.v

Splitting register file into separate pieces

2015-04-23 18:07:50 -04:00

ecfg_if.v

Splitting register file (rx,tx,base)

2015-04-23 17:50:45 -04:00

ecfg_rx.v

Splitting register file (rx,tx,base)

2015-04-23 17:50:45 -04:00

ecfg_tx.v

Verilator based lint cleanup

2015-04-23 18:57:55 -04:00

ecfg.v

Message box working...

2015-04-19 21:55:07 -04:00

eclocks.v

Verilator based lint cleanup

2015-04-23 18:57:55 -04:00

elink_constants.v

Renaming constants file

2015-04-22 13:56:48 -04:00

elink_regmap.v

Adding DMA register to regmap

2015-04-23 18:08:52 -04:00

elink.v

Changing so basic elink unti is without AXI

2015-04-23 18:08:20 -04:00

emaxi.v

Bug fix, missing pipeline stage on read response

2015-04-21 17:14:30 -04:00

ememory.v

Changing to packet interface

2015-04-23 18:07:27 -04:00

ereset.v

Cleanup

2015-04-18 16:26:32 -04:00

erx_disty.v

Adding reset to critical signals in pipe

2015-04-23 20:06:11 -04:00

erx_io.v

Verilator based lint cleanup

2015-04-23 18:57:55 -04:00

erx_protocol.v

Fixed floating net bug

2015-04-23 20:05:00 -04:00

erx.v

Verilator based lint cleanup

2015-04-23 18:57:55 -04:00

esaxi.v

File cleanup

2015-04-23 18:10:07 -04:00

etx_arbiter.v

Packet interface change

2015-04-23 17:57:24 -04:00

etx_io.v

Clarified lclk names

2015-04-22 15:03:24 -04:00

etx_protocol.v

Verilator based lint cleanup

2015-04-23 18:57:55 -04:00

etx.v

Verilator based lint cleanup

2015-04-23 18:57:55 -04:00